From 97912b1a2954d5237e88ceb9c8ed7bb88bd690f7 Mon Sep 17 00:00:00 2001 From: "(Tim) Efthimis Kritikos" Date: Tue, 16 May 2023 13:59:16 +0100 Subject: [PATCH] Fixed bug found by icarus verilog and added outdated notice to README --- README.md | 1 + system/processor.v | 2 +- 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/README.md b/README.md index 9281f72..4df92f9 100644 --- a/README.md +++ b/README.md @@ -28,6 +28,7 @@ Specifically this list shows the software needed and the versions used during de After that you can run `make` on the top level directory and it should build everything and start the simulation ### High level design overview +This image is outdated. It was made for v0.1.0 9086 logo ### License diff --git a/system/processor.v b/system/processor.v index 3bb99c0..a55bdee 100644 --- a/system/processor.v +++ b/system/processor.v @@ -195,6 +195,7 @@ always @(negedge reset) begin end always @(posedge reset) begin proc_state <= `PROC_RESET; + valid_instruction_ack <= 0; // needs early init end /*** Processor stages ***/ @@ -214,7 +215,6 @@ always @(posedge clock) begin SIMPLE_MICRO <= 0; proc_state <= `PROC_DE_STATE_ENTRY; owe_set_init <= 0; - valid_instruction_ack <= 0; end `PROC_DE_STATE_ENTRY:begin if(VALID_INSTRUCTION==1 || SIMPLE_MICRO == 1 ) begin