Fixed bug found by icarus verilog and added outdated notice to README
This commit is contained in:
parent
bfa576e2a0
commit
97912b1a29
@ -28,6 +28,7 @@ Specifically this list shows the software needed and the versions used during de
|
|||||||
After that you can run `make` on the top level directory and it should build everything and start the simulation
|
After that you can run `make` on the top level directory and it should build everything and start the simulation
|
||||||
|
|
||||||
### High level design overview
|
### High level design overview
|
||||||
|
This image is outdated. It was made for v0.1.0
|
||||||
<img width="700" style=" margin: 10px 0px 10px 10px;" alt="9086 logo" src="readme_files/9086_overview.svg">
|
<img width="700" style=" margin: 10px 0px 10px 10px;" alt="9086 logo" src="readme_files/9086_overview.svg">
|
||||||
|
|
||||||
### License
|
### License
|
||||||
|
@ -195,6 +195,7 @@ always @(negedge reset) begin
|
|||||||
end
|
end
|
||||||
always @(posedge reset) begin
|
always @(posedge reset) begin
|
||||||
proc_state <= `PROC_RESET;
|
proc_state <= `PROC_RESET;
|
||||||
|
valid_instruction_ack <= 0; // needs early init
|
||||||
end
|
end
|
||||||
|
|
||||||
/*** Processor stages ***/
|
/*** Processor stages ***/
|
||||||
@ -214,7 +215,6 @@ always @(posedge clock) begin
|
|||||||
SIMPLE_MICRO <= 0;
|
SIMPLE_MICRO <= 0;
|
||||||
proc_state <= `PROC_DE_STATE_ENTRY;
|
proc_state <= `PROC_DE_STATE_ENTRY;
|
||||||
owe_set_init <= 0;
|
owe_set_init <= 0;
|
||||||
valid_instruction_ack <= 0;
|
|
||||||
end
|
end
|
||||||
`PROC_DE_STATE_ENTRY:begin
|
`PROC_DE_STATE_ENTRY:begin
|
||||||
if(VALID_INSTRUCTION==1 || SIMPLE_MICRO == 1 ) begin
|
if(VALID_INSTRUCTION==1 || SIMPLE_MICRO == 1 ) begin
|
||||||
|
Loading…
Reference in New Issue
Block a user