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Added the SUB instruction (piggybacking off of ADD) AND THE COMPILER FINISHES GENERATING CODE!!

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(Tim) Efthimis Kritikos 2023-02-24 12:18:17 +00:00
parent 808827cbdd
commit 96b7a4d298
1 changed files with 12 additions and 2 deletions
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14
system/decoder.v
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@ -110,9 +110,12 @@ always @( CIR or SIMPLE_MICRO or seq_addr_input ) begin
end end
endcase endcase
end end
11'b1000_00xx_000 : begin 11'b1000_00xx_101, /* SUB */
11'b1000_00xx_000 : /* ADD */ begin
/* ADD - Add Immediate word/byte to register/memory */ /* ADD - Add Immediate word/byte to register/memory */
/* 1 0 0 0 0 0 S W | MOD 0 0 0 R/M | < DISP LO > | < DISP HI > | DATA | DATA if W | */ /* 1 0 0 0 0 0 S W | MOD 0 0 0 R/M | < DISP LO > | < DISP HI > | DATA | DATA if W | */
/* SUB - Subtract mmediate word/byte from register/memory */
/* 1 0 0 0 0 0 S W | MOD 0 0 0 R/M | < DISP LO > | < DISP HI > | DATA | DATA if W | */
opcode_size=1; opcode_size=1;
has_operands=1; has_operands=1;
Wbit=CIR[8:8]; Wbit=CIR[8:8];
@ -124,7 +127,6 @@ always @( CIR or SIMPLE_MICRO or seq_addr_input ) begin
OUT_MOD={1'b0,IN_MOD}; OUT_MOD={1'b0,IN_MOD};
reg_read_port2_addr={Wbit,RM}; reg_read_port2_addr={Wbit,RM};
reg_write_addr={Wbit,RM}; reg_write_addr={Wbit,RM};
ALU_1OP=`ALU_OP_ADD;
case({Sbit,Wbit}) case({Sbit,Wbit})
2'b00,2'b11:begin 2'b00,2'b11:begin
`start_unaligning_instruction `start_unaligning_instruction
@ -138,6 +140,14 @@ always @( CIR or SIMPLE_MICRO or seq_addr_input ) begin
`invalid_instruction `invalid_instruction
end end
endcase endcase
case(CIR[5:3])
3'b000: ALU_1OP=`ALU_OP_ADD;
3'b101: ALU_1OP=`ALU_OP_SUB_REVERSE;
default:begin
/*Should be impossible*/
`invalid_instruction
end
endcase
end end
11'b1000_00xx_111 : begin 11'b1000_00xx_111 : begin
/* CMP - compare Immediate with register / memory */ /* CMP - compare Immediate with register / memory */