From 96b7a4d2980e652a58e4c7112681125043ffc15f Mon Sep 17 00:00:00 2001 From: "(Tim) Efthimis Kritikos" Date: Fri, 24 Feb 2023 12:18:17 +0000 Subject: [PATCH] Added the SUB instruction (piggybacking off of ADD) AND THE COMPILER FINISHES GENERATING CODE!! --- system/decoder.v | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) diff --git a/system/decoder.v b/system/decoder.v index c1c8ea2..faef720 100644 --- a/system/decoder.v +++ b/system/decoder.v @@ -110,9 +110,12 @@ always @( CIR or SIMPLE_MICRO or seq_addr_input ) begin end endcase end - 11'b1000_00xx_000 : begin + 11'b1000_00xx_101, /* SUB */ + 11'b1000_00xx_000 : /* ADD */ begin /* ADD - Add Immediate word/byte to register/memory */ /* 1 0 0 0 0 0 S W | MOD 0 0 0 R/M | < DISP LO > | < DISP HI > | DATA | DATA if W | */ + /* SUB - Subtract mmediate word/byte from register/memory */ + /* 1 0 0 0 0 0 S W | MOD 0 0 0 R/M | < DISP LO > | < DISP HI > | DATA | DATA if W | */ opcode_size=1; has_operands=1; Wbit=CIR[8:8]; @@ -124,7 +127,6 @@ always @( CIR or SIMPLE_MICRO or seq_addr_input ) begin OUT_MOD={1'b0,IN_MOD}; reg_read_port2_addr={Wbit,RM}; reg_write_addr={Wbit,RM}; - ALU_1OP=`ALU_OP_ADD; case({Sbit,Wbit}) 2'b00,2'b11:begin `start_unaligning_instruction @@ -138,6 +140,14 @@ always @( CIR or SIMPLE_MICRO or seq_addr_input ) begin `invalid_instruction end endcase + case(CIR[5:3]) + 3'b000: ALU_1OP=`ALU_OP_ADD; + 3'b101: ALU_1OP=`ALU_OP_SUB_REVERSE; + default:begin + /*Should be impossible*/ + `invalid_instruction + end + endcase end 11'b1000_00xx_111 : begin /* CMP - compare Immediate with register / memory */