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Fixed ALU bug and added missed updates to the Wbit

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(Tim) Efthimis Kritikos 2023-02-12 01:28:37 +00:00
parent c684348e38
commit 923bf07c72
3 changed files with 20 additions and 7 deletions
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24
cpu/alu.v
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@ -6,13 +6,23 @@ reg C_FLAG;
assign FLAGS={(Wbit==1)?OUT[15:15]:OUT[7:7],(Wbit==1) ? (OUT[15:0]=='h0000) : (OUT[7:0]=='h00),5'b00000,C_FLAG};
always @ ( * ) begin
case (op)
`ALU_OP_ADD: {C_FLAG,OUT}=A+B;
`ALU_OP_SUB: {C_FLAG,OUT}=A-B;
`ALU_OP_AND: OUT=A&B;
`ALU_OP_OR: OUT=A|B;
`ALU_OP_XOR: OUT=A^B;
endcase
if(Wbit==1)begin
case (op)
`ALU_OP_ADD: {C_FLAG,OUT}=A+B;
`ALU_OP_SUB: {C_FLAG,OUT}=A-B;
`ALU_OP_AND: OUT=A&B;
`ALU_OP_OR: OUT=A|B;
`ALU_OP_XOR: OUT=A^B;
endcase
end else begin
case (op)
`ALU_OP_ADD: {C_FLAG,OUT[7:0]}=A[7:0]+B[7:0];
`ALU_OP_SUB: {C_FLAG,OUT[7:0]}=A[7:0]-B[7:0];
`ALU_OP_AND: OUT=A&B;
`ALU_OP_OR: OUT=A|B;
`ALU_OP_XOR: OUT=A^B;
endcase
end
end
endmodule

3
cpu/processor.v
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@ -220,6 +220,7 @@ always @(posedge clock) begin
/* Add Immediate word/byte to register/memory */
/* 1 0 0 0 0 0 S W | MOD 0 0 0 R/M | < DISP LO > | < DISP HI > | DATA | DATA if W | */
`start_aligning_instruction
Wbit=CIR[8:8];
IN_MOD=2'b11;
in1_sel=2'b00;
in2_sel=2'b01;
@ -321,6 +322,7 @@ always @(posedge clock) begin
/* INC - Increment Register */
/* | 0 1 0 0 0 REG | */
`start_unaligning_instruction
Wbit=1;
in1_sel=2'b01;
in2_sel=2'b00;
out_sel=2'b11;
@ -344,6 +346,7 @@ always @(posedge clock) begin
/* INC - Register/Memory */
/* 1 1 1 1 1 1 1 W | MOD 0 0 0 R/M | < DISP LO> | < DISP HI> */
`start_aligning_instruction
Wbit=CIR[8:8];
IN_MOD=CIR[7:6];
in1_sel=2'b00;/* number 1 */
in2_sel=(CIR[7:6]==2'b11)? 2'b01 : 2'b00;

0
cpu/xt2 Normal file
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