diff --git a/cpu/alu.v b/cpu/alu.v index ec38d1e..ce0da79 100644 --- a/cpu/alu.v +++ b/cpu/alu.v @@ -6,13 +6,23 @@ reg C_FLAG; assign FLAGS={(Wbit==1)?OUT[15:15]:OUT[7:7],(Wbit==1) ? (OUT[15:0]=='h0000) : (OUT[7:0]=='h00),5'b00000,C_FLAG}; always @ ( * ) begin - case (op) - `ALU_OP_ADD: {C_FLAG,OUT}=A+B; - `ALU_OP_SUB: {C_FLAG,OUT}=A-B; - `ALU_OP_AND: OUT=A&B; - `ALU_OP_OR: OUT=A|B; - `ALU_OP_XOR: OUT=A^B; - endcase + if(Wbit==1)begin + case (op) + `ALU_OP_ADD: {C_FLAG,OUT}=A+B; + `ALU_OP_SUB: {C_FLAG,OUT}=A-B; + `ALU_OP_AND: OUT=A&B; + `ALU_OP_OR: OUT=A|B; + `ALU_OP_XOR: OUT=A^B; + endcase + end else begin + case (op) + `ALU_OP_ADD: {C_FLAG,OUT[7:0]}=A[7:0]+B[7:0]; + `ALU_OP_SUB: {C_FLAG,OUT[7:0]}=A[7:0]-B[7:0]; + `ALU_OP_AND: OUT=A&B; + `ALU_OP_OR: OUT=A|B; + `ALU_OP_XOR: OUT=A^B; + endcase + end end endmodule diff --git a/cpu/processor.v b/cpu/processor.v index 3dd4a1e..cfb5ebe 100644 --- a/cpu/processor.v +++ b/cpu/processor.v @@ -220,6 +220,7 @@ always @(posedge clock) begin /* Add Immediate word/byte to register/memory */ /* 1 0 0 0 0 0 S W | MOD 0 0 0 R/M | < DISP LO > | < DISP HI > | DATA | DATA if W | */ `start_aligning_instruction + Wbit=CIR[8:8]; IN_MOD=2'b11; in1_sel=2'b00; in2_sel=2'b01; @@ -321,6 +322,7 @@ always @(posedge clock) begin /* INC - Increment Register */ /* | 0 1 0 0 0 REG | */ `start_unaligning_instruction + Wbit=1; in1_sel=2'b01; in2_sel=2'b00; out_sel=2'b11; @@ -344,6 +346,7 @@ always @(posedge clock) begin /* INC - Register/Memory */ /* 1 1 1 1 1 1 1 W | MOD 0 0 0 R/M | < DISP LO> | < DISP HI> */ `start_aligning_instruction + Wbit=CIR[8:8]; IN_MOD=CIR[7:6]; in1_sel=2'b00;/* number 1 */ in2_sel=(CIR[7:6]==2'b11)? 2'b01 : 2'b00; diff --git a/cpu/xt2 b/cpu/xt2 new file mode 100644 index 0000000..e69de29