Build system: Improved the handling of seeds, moved most of the board specific build instructions to the board specific .mk file and fixed bios.asm dependencies
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2
.gitignore
vendored
2
.gitignore
vendored
@ -10,7 +10,6 @@
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*.bit
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*.fst.hier
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abc.history
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system/synth_ecp5_out.config
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boot_code/*.bin
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boot_code/*.txt
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boot_code/*.stxt
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@ -18,5 +17,6 @@ system/boot_code.bin
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system/boot_code.txt
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system/obj_dir/
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system/simplified_ucode.txt
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system/build/
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tools/*svg
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system/external_ip/litedram_core_ecp5_phy.v
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@ -12,7 +12,7 @@ brainfuck_interpreted.bin: brainfuck_interpreter_v0.asm hello_9086.bf.asm dos_la
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brainfuck_compiled.bin: brainfuck_compiler_v1.asm hello_9086.bf.asm dos_layer.asm
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brainfuck_mandelbrot.bin: brainfuck_compiler_v1.asm mandelbrot.bf.asm dos_layer.asm
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colored_led.bin: dos_layer.asm
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bios.bin: LiteDram_init.asm brainfuck_compiler_v1.asm
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bios.bin: LiteDram_init.asm brainfuck_compiler_v1.asm hello_9086.bf.asm dos_layer.asm
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fibonacci.bin: helpers.asm
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gnome_sort.bin: helpers.asm
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10
common.mk
10
common.mk
@ -16,9 +16,17 @@ NUMACTL=#numactl -m 0 -C 0,1 --
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######## SYNTHESIS OPTIONS ########
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FPGA_BOARD=OrangeCrab_r0.2.1
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# BOARD: the options are the directories in system/fpga_config/.
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# Select the one you have
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FPGA_BOARD=OrangeCrab_r0.2.1
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# If this options is set to 1, builds with different seeds will be
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# considered separate, in combination with the fact that this build
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# system by default is generating a new seed for each build, it means
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# that for each build a new set of files gets created in the build
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# directory with the seed number on the filename without overwriting
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# the old ones.
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BUILD_SEED_DIFFERENTIATION=0
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VERSION="v0.3.0-dev"
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125
system/Makefile
125
system/Makefile
@ -15,20 +15,26 @@
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# You should have received a copy of the GNU General Public License
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# along with this program. If not, see <http://www.gnu.org/licenses/>.
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#
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TOP_LEVEL_SOURCE=system.v #TODO I really don't like this variable and its name
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SOURCES=processor.v memory.v registers.v alu.v decoder.v general.v biu.v execute.v
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EVENT_SIM_TESTBENCH=testbench.v
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VERILATOR_TESTBENCH=testbench.cpp
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INCLUDES=exec_state_def.v alu_header.v config.v ucode_header.v error_header.v
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SYSTEM_VVP=system.vvp
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VERILATOR_BIN=obj_dir/Vsystem
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BOOT_CODE=boot_code.txt
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GTKWSAVE=../gtkwave_savefile.gtkw
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MICROCODE=ucode.txt
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NO_ASM=0
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include ../common.mk
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################################################################################
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#### SIMULATION RECIPES ####
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################################################################################
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EVENT_SIM_TESTBENCH=testbench.v
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VERILATOR_TESTBENCH=testbench.cpp
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SIMULATION_TOP_LEVEL_SOURCE=system.v
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GTKWSAVE=../gtkwave_savefile.gtkw
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VERILATOR_BIN=obj_dir/Vsystem
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SYSTEM_VVP=system.vvp
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#build options
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VERILATOR_OPTS += --cc --exe
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@ -44,17 +50,31 @@ VERILATOR_OPTS += -x-assign fast --x-initial fast
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#VERILATOR_OPTS += -x-assign unique --x-initial unique
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# COMPILING
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${SYSTEM_VVP} : ${TOP_LEVEL_SOURCE} ${SOURCES} ${INCLUDES} ${EVENT_SIM_TESTBENCH}
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${SYSTEM_VVP} : ${SIMULATION_TOP_LEVEL_SOURCE} ${SOURCES} ${INCLUDES} ${EVENT_SIM_TESTBENCH}
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${QUIET_IVERILOG}
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${Q}iverilog -g2012 -D CALCULATE_IPC -D OUTPUT_JSON_STATISTICS -o "$@" ${TOP_LEVEL_SOURCE} ${SOURCES} ${EVENT_SIM_TESTBENCH}
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${Q}iverilog -g2012 -D CALCULATE_IPC -D OUTPUT_JSON_STATISTICS -o "$@" ${SIMULATION_TOP_LEVEL_SOURCE} ${SOURCES} ${EVENT_SIM_TESTBENCH}
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${VERILATOR_BIN}: ${VERILATOR_BIN}.mk
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${Q}make ${MAKEOPTS} OPT_FAST="-O2 -march=native -mtune=native" -C obj_dir -f ../verilator_makefile Vsystem
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${VERILATOR_BIN}.mk: ${VERILATOR_TESTBENCH} ${TOP_LEVEL_SOURCE} ${SOURCES} ${INCLUDES}
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${VERILATOR_BIN}.mk: ${VERILATOR_TESTBENCH} ${SIMULATION_TOP_LEVEL_SOURCE} ${SOURCES} ${INCLUDES}
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${QUIET_VERILATOR}
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${Q}verilator -DCALCULATE_IPC -DOUTPUT_JSON_STATISTICS ${VERILATOR_OPTS} $^
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################################################################################
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#### FPGA/ASIC RECIPES ####
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################################################################################
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BUILD_FILES_PREFIX=build/
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$(shell mkdir -p $(BUILD_FILES_PREFIX))
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FPGA_SEED ::= $(shell seq 1 200|sort -R|head -n1)
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ifeq "${BUILD_SEED_DIFFERENTIATION}" "1"
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BUILD_NAME=${FPGA_BOARD}_${FPGA_SEED}
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else
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BUILD_NAME=${FPGA_BOARD}
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endif
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include fpga_config/${FPGA_BOARD}/config.mk
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# Synthesis and bitstream creation for ECP5
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@ -66,55 +86,60 @@ else
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$(error invalid ECP5 device ${ECP5_DEVICE})
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endif
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ECP5_TARGETS=synth_ecp5.json synth_ecp5_out.config synth_ecp5.bit synth_ecp5.dfu synth_pnr_report.json
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ECP5_TARGETS+=abc.history # created from yosys
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EXTRA_SYNTHESIS_SOURCES=peripherals/I2C_driver.v peripherals/ascii_to_HD44780_driver.v peripherals/pcf8574_for_HD44780.v peripherals/Wishbone_IO_driver.v peripherals/Wishbone_memory_driver.v
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EXTERNAL_IP_SOURCES=external_ip/litedram_core_ecp5_phy.v
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simplified_ucode.txt:ucode.txt
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${Q}tr 'x' '0' < $^ | sed 's@//.*@@' | grep ^@ |sort | sed 's/.* .//;s/ $$//' | tr -d _ > $@
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#TODO: we are relying on yosys to trim the input program txt file and hope its enough for the whole program...
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synth_ecp5.json: ${SOURCES} fpga_config/${FPGA_BOARD}/fpga_top.v ${EXTRA_SYNTHESIS_SOURCES} ${EXTERNAL_IP_SOURCES} ${INCLUDES} ../boot_code/bios.stxt simplified_ucode.txt
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${QUIET_YOSYS}
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${Q} yosys -q -p 'read_verilog -defer -noautowire -sv '"${SOURCES} fpga_config/${FPGA_BOARD}/fpga_top.v ${EXTRA_SYNTHESIS_SOURCES} ${EXTERNAL_IP_SOURCES}; attrmap -tocase keep -imap keep="true" keep=1 -imap keep="false" keep=0 -remove keep=0; synth_ecp5 -json $@ -abc9 -top fpga_top"
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NEXTPNR_SEED ::= $(shell seq 1 200|sort -R|head -n1)
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synth_ecp5_out.config:synth_ecp5.json
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${QUIET_NEXTPNR}
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${Q}printf '\e[1;30mNotice: nextpnr rng seed is : %s\e[0m\n' "${NEXTPNR_SEED}"
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${Q} nextpnr-ecp5 --threads 5 --timing-allow-fail --seed ${NEXTPNR_SEED} --Werror -q --json $< --textcfg $@.1 ${NEXTPNR_ECP5_DEV} --package ${ECP5_PACKAGE} --speed 8 --lpf fpga_config/${FPGA_BOARD}/pin_constraint.pcf --report=synth_pnr_report.json
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${Q}../tools/parse_nextpnr_stats.sh --brief synth_pnr_report.json
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${Q}mv "$@.1" "$@"
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synth_ecp5.bit:synth_ecp5_out.config
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${QUIET_ECPPACK}
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${Q}ecppack --compress --freq 38.8 --input $< --bit $@
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synth_ecp5.dfu:synth_ecp5.bit
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${QUIET_DFU_SUFFIX}
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${Q}cp "$<" synth_ecp5.temp_dfu
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@#From some testing, dfu-suffix does output errors to stderr so this should be fine
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${Q}dfu-suffix --vid 1209 --pid 5af0 --add synth_ecp5.temp_dfu > /dev/null
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${Q}mv synth_ecp5.temp_dfu "$@"
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upload_orangecrab:synth_ecp5.dfu
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${QUIET_DFU_UTIL}
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${Q}stdbuf -o0 dfu-util --download "$<" |stdbuf -o0 tr '\n' '\a' | stdbuf -o0 tr '\r' '\n' | grep Download --line-buffered | stdbuf -o0 tr '\n' '\r' |stdbuf -o0 tr '\a' '\n'
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nextpnr-gui: synth_ecp5.json
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${QUIET_NEXTPNR}
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${Q} nextpnr-ecp5 --seed ${NEXTPNR_SEED} --json $< ${NEXTPNR_ECP5_DEV} --package ${ECP5_PACKAGE} --speed 8 --lpf fpga_config/${FPGA_BOARD}/pin_constraint.pcf --gui
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external_ip/litedram_core_ecp5_phy.v:
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${QUIET_DOWNLOAD}
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${Q}../tools/gen_litedram.sh -q "$@"
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upload: upload_orangecrab
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#########################################
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## SYNTHESIS RECIPES
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SYNTHESIS_SOURCES ::= ${SOURCES} fpga_config/${FPGA_BOARD}/fpga_top.v ${SOC_SYNTHESIS_SOURCES} ${INCLUDES}
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#TODO: we are relying on yosys to trim the input program txt file and hope its enough for the whole program...
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${BUILD_FILES_PREFIX}synth_ecp5_${FPGA_BOARD}.json: ${SYNTHESIS_SOURCES} ${FPGA_BOOTCODE} simplified_ucode.txt
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${QUIET_YOSYS}
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${Q} yosys -q -p 'read_verilog -defer -noautowire -sv '"${SYNTHESIS_SOURCES}; attrmap -tocase keep -imap keep="true" keep=1 -imap keep="false" keep=0 -remove keep=0; synth_ecp5 -json \"$@\" -abc9 -top fpga_top"
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##########################################
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## PLACE AND ROUTE RECIPES
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${BUILD_FILES_PREFIX}nextpnr_${BUILD_NAME}.bit:${BUILD_FILES_PREFIX}synth_${FPGA_BOARD}.json
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${QUIET_NEXTPNR}
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${Q}printf '\e[1;30mNotice: nextpnr rng seed is : %s\e[0m\n' "${FPGA_SEED}"
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${Q} nextpnr-ecp5 --seed ${FPGA_SEED} --Werror -q --json $< --textcfg "$@_config_temp" ${NEXTPNR_ECP5_DEV} --package ${ECP5_PACKAGE} --speed ${ECP5_SPEED_GRADE} --lpf fpga_config/${FPGA_BOARD}/pin_constraint.pcf --report=${BUILD_FILES_PREFIX}nextpnr_report_${BUILD_NAME}.json
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${Q}../tools/parse_nextpnr_stats.sh --brief ${BUILD_FILES_PREFIX}nextpnr_report_${BUILD_NAME}.json
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${Q}mv "$@_config_temp" "$@_config" # nextpnr-ecp5 will still generate a file even if it fails breaking the assumptions of the build system.
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${QUIET_ECPPACK}
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${Q}ecppack --compress --freq 38.8 --input $@_config --bit $@
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nextpnr-gui: ${BUILD_FILES_PREFIX}synth_${FPGA_BOARD}.json
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${QUIET_NEXTPNR}
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${Q} nextpnr-ecp5 --seed ${FPGA_SEED} --json $< ${NEXTPNR_ECP5_DEV} --package ${ECP5_PACKAGE} --speed ${ECP5_SPEED_GRADE} --lpf fpga_config/${FPGA_BOARD}/pin_constraint.pcf --gui
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##########################################
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## BITSTREAM MODIFICATION FOR/AND UPLOADING
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${BUILD_FILES_PREFIX}bitstream_${BUILD_NAME}.dfu:${BUILD_FILES_PREFIX}bitstream_${BUILD_NAME}.bit
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${QUIET_DFU_SUFFIX}
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${Q}cp "$<" "$<.tempdfu"
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@#From some testing, dfu-suffix does output errors to stderr so this should be fine
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${Q}dfu-suffix --vid 1209 --pid 5af0 --add "$<.tempdfu" > /dev/null
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${Q}mv "$<.tempdfu" "$@"
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dfu_upload:${BUILD_FILES_PREFIX}bitstream_${BUILD_NAME}.dfu
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${QUIET_DFU_UTIL}
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${Q}stdbuf -o0 dfu-util --download "$<" |stdbuf -o0 tr '\n' '\a' | stdbuf -o0 tr '\r' '\n' | grep Download --line-buffered | stdbuf -o0 tr '\n' '\r' |stdbuf -o0 tr '\a' '\n'
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################################################################################
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#### CLEAN-UP ####
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################################################################################
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.PHONY: clean
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clean:
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$(call QUIET_CLEAN,system)
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${Q}rm -rf ${SYSTEM_VVP} *.fst boot_code.txt boot_code.bin *memdump *memdumptxt obj_dir *json simplified_ucode.txt ${ECP5_TARGETS}
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${Q}rm -rf ${SYSTEM_VVP} *.fst boot_code.txt boot_code.bin *memdump *memdumptxt obj_dir simplified_ucode.txt abc.history build
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@ -5,3 +5,27 @@ ECP5_DEVICE=25F
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# 85F: Create bitstream for the LFE5U-85F
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ECP5_PACKAGE=CSFBGA285
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# ECP5_PACKAGE: CSFBGA285: The one used in OrangeCrab
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FPGA_FILE_EXT=dfu
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#This is on the 8th postiion in the chip id, for example
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# LFE5U-25-7BG381I
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# ^---------- this would be a 7 speed grade
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#
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# 6 is the slowest and 8 is the fastest
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ECP5_SPEED_GRADE=8
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######## End fo user configuration ########
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SOC_SYNTHESIS_SOURCES=peripherals/I2C_driver.v peripherals/ascii_to_HD44780_driver.v peripherals/pcf8574_for_HD44780.v peripherals/Wishbone_IO_driver.v peripherals/Wishbone_memory_driver.v external_ip/litedram_core_ecp5_phy.v
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FPGA_BOOTCODE=../boot_code/bios.stxt
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upload: dfu_upload
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${BUILD_FILES_PREFIX}bitstream_${BUILD_NAME}.bit:${BUILD_FILES_PREFIX}nextpnr_${BUILD_NAME}.bit
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${Q}cp "$^" "$@"
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${BUILD_FILES_PREFIX}synth_${FPGA_BOARD}.json:${BUILD_FILES_PREFIX}synth_ecp5_${FPGA_BOARD}.json
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${Q}cp "$^" "$@"
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