Build system: Improved the handling of seeds, moved most of the board specific build instructions to the board specific .mk file and fixed bios.asm dependencies

.gitignore

@@ -10,7 +10,6 @@
 *.bit
 *.fst.hier
 abc.history
-system/synth_ecp5_out.config
 boot_code/*.bin
 boot_code/*.txt
 boot_code/*.stxt
@@ -18,5 +17,6 @@ system/boot_code.bin
 system/boot_code.txt
 system/obj_dir/
 system/simplified_ucode.txt
+system/build/
 tools/*svg
 system/external_ip/litedram_core_ecp5_phy.v

boot_code/Makefile

@@ -12,7 +12,7 @@ brainfuck_interpreted.bin: brainfuck_interpreter_v0.asm hello_9086.bf.asm dos_la
 brainfuck_compiled.bin: brainfuck_compiler_v1.asm hello_9086.bf.asm dos_layer.asm
 brainfuck_mandelbrot.bin: brainfuck_compiler_v1.asm mandelbrot.bf.asm dos_layer.asm
 colored_led.bin: dos_layer.asm
-bios.bin: LiteDram_init.asm brainfuck_compiler_v1.asm
+bios.bin: LiteDram_init.asm brainfuck_compiler_v1.asm hello_9086.bf.asm dos_layer.asm
 
 fibonacci.bin: helpers.asm
 gnome_sort.bin: helpers.asm

common.mk

@@ -16,9 +16,17 @@ NUMACTL=#numactl -m 0 -C 0,1 --
 
 ######## SYNTHESIS OPTIONS ########
 
-FPGA_BOARD=OrangeCrab_r0.2.1
 # BOARD: the options are the directories in system/fpga_config/.
 #        Select the one you have
+FPGA_BOARD=OrangeCrab_r0.2.1
+
+# If this options is set to 1, builds with different seeds will be
+# considered separate, in combination with the fact that this build
+# system by default is generating a new seed for each build, it means
+# that for each build a new set of files gets created in the build 
+# directory with the seed number on the filename without overwriting
+# the old ones.
+BUILD_SEED_DIFFERENTIATION=0
 
 VERSION="v0.3.0-dev"
 

system/Makefile

@@ -15,20 +15,26 @@
 #   You should have received a copy of the GNU General Public License
 #   along with this program.  If not, see <http://www.gnu.org/licenses/>.
 #
-TOP_LEVEL_SOURCE=system.v #TODO I really don't like this variable and its name
+
 SOURCES=processor.v memory.v registers.v alu.v decoder.v general.v biu.v execute.v
-EVENT_SIM_TESTBENCH=testbench.v
-VERILATOR_TESTBENCH=testbench.cpp
 INCLUDES=exec_state_def.v alu_header.v config.v ucode_header.v error_header.v
-SYSTEM_VVP=system.vvp
-VERILATOR_BIN=obj_dir/Vsystem
 BOOT_CODE=boot_code.txt
-GTKWSAVE=../gtkwave_savefile.gtkw
 MICROCODE=ucode.txt
 
 NO_ASM=0
 include ../common.mk
 
+################################################################################
+####                           SIMULATION RECIPES                           ####
+################################################################################
+
+EVENT_SIM_TESTBENCH=testbench.v
+VERILATOR_TESTBENCH=testbench.cpp
+SIMULATION_TOP_LEVEL_SOURCE=system.v
+GTKWSAVE=../gtkwave_savefile.gtkw
+VERILATOR_BIN=obj_dir/Vsystem
+SYSTEM_VVP=system.vvp
+
 #build options
 VERILATOR_OPTS += --cc --exe
 
@@ -44,17 +50,31 @@ VERILATOR_OPTS += -x-assign fast --x-initial fast
 #VERILATOR_OPTS += -x-assign unique --x-initial unique
 
 # COMPILING
-${SYSTEM_VVP} : ${TOP_LEVEL_SOURCE} ${SOURCES} ${INCLUDES} ${EVENT_SIM_TESTBENCH}
+${SYSTEM_VVP} : ${SIMULATION_TOP_LEVEL_SOURCE} ${SOURCES} ${INCLUDES} ${EVENT_SIM_TESTBENCH}
 	${QUIET_IVERILOG}
-	${Q}iverilog -g2012 -D CALCULATE_IPC -D OUTPUT_JSON_STATISTICS -o "$@" ${TOP_LEVEL_SOURCE} ${SOURCES} ${EVENT_SIM_TESTBENCH}
+	${Q}iverilog -g2012 -D CALCULATE_IPC -D OUTPUT_JSON_STATISTICS -o "$@" ${SIMULATION_TOP_LEVEL_SOURCE} ${SOURCES} ${EVENT_SIM_TESTBENCH}
 
 ${VERILATOR_BIN}: ${VERILATOR_BIN}.mk
 	${Q}make ${MAKEOPTS} OPT_FAST="-O2 -march=native -mtune=native" -C obj_dir -f ../verilator_makefile Vsystem
 
-${VERILATOR_BIN}.mk: ${VERILATOR_TESTBENCH} ${TOP_LEVEL_SOURCE} ${SOURCES} ${INCLUDES}
+${VERILATOR_BIN}.mk: ${VERILATOR_TESTBENCH} ${SIMULATION_TOP_LEVEL_SOURCE} ${SOURCES} ${INCLUDES}
 	${QUIET_VERILATOR}
 	${Q}verilator -DCALCULATE_IPC -DOUTPUT_JSON_STATISTICS ${VERILATOR_OPTS} $^
 
+################################################################################
+####                           FPGA/ASIC RECIPES                            ####
+################################################################################
+
+BUILD_FILES_PREFIX=build/
+$(shell mkdir -p $(BUILD_FILES_PREFIX))
+FPGA_SEED ::= $(shell seq 1 200|sort -R|head -n1)
+
+ifeq "${BUILD_SEED_DIFFERENTIATION}" "1"
+BUILD_NAME=${FPGA_BOARD}_${FPGA_SEED}
+else
+BUILD_NAME=${FPGA_BOARD}
+endif
+
 include fpga_config/${FPGA_BOARD}/config.mk
 
 # Synthesis and bitstream creation for ECP5
@@ -66,55 +86,60 @@ else
 $(error invalid ECP5 device ${ECP5_DEVICE})
 endif
 
-ECP5_TARGETS=synth_ecp5.json synth_ecp5_out.config synth_ecp5.bit synth_ecp5.dfu synth_pnr_report.json
-ECP5_TARGETS+=abc.history # created from yosys
-
-EXTRA_SYNTHESIS_SOURCES=peripherals/I2C_driver.v peripherals/ascii_to_HD44780_driver.v peripherals/pcf8574_for_HD44780.v peripherals/Wishbone_IO_driver.v peripherals/Wishbone_memory_driver.v
-EXTERNAL_IP_SOURCES=external_ip/litedram_core_ecp5_phy.v
-
 simplified_ucode.txt:ucode.txt
 	${Q}tr 'x' '0' < $^ | sed 's@//.*@@' | grep ^@ |sort | sed 's/.* .//;s/ $$//' | tr -d _ > $@
 
-#TODO: we are relying on yosys to trim the input program txt file and hope its enough for the whole program...
-synth_ecp5.json: ${SOURCES} fpga_config/${FPGA_BOARD}/fpga_top.v ${EXTRA_SYNTHESIS_SOURCES} ${EXTERNAL_IP_SOURCES} ${INCLUDES} ../boot_code/bios.stxt simplified_ucode.txt
-	${QUIET_YOSYS}
-	${Q} yosys -q -p 'read_verilog -defer -noautowire -sv '"${SOURCES} fpga_config/${FPGA_BOARD}/fpga_top.v ${EXTRA_SYNTHESIS_SOURCES} ${EXTERNAL_IP_SOURCES}; attrmap -tocase keep -imap keep="true" keep=1 -imap keep="false" keep=0 -remove keep=0; synth_ecp5 -json $@ -abc9 -top fpga_top"
-
-NEXTPNR_SEED ::= $(shell seq 1 200|sort -R|head -n1)
-
-synth_ecp5_out.config:synth_ecp5.json
-	${QUIET_NEXTPNR}
-	${Q}printf '\e[1;30mNotice: nextpnr rng seed is : %s\e[0m\n' "${NEXTPNR_SEED}"
-	${Q} nextpnr-ecp5 --threads 5 --timing-allow-fail --seed ${NEXTPNR_SEED} --Werror -q --json $< --textcfg $@.1 ${NEXTPNR_ECP5_DEV} --package ${ECP5_PACKAGE} --speed 8 --lpf fpga_config/${FPGA_BOARD}/pin_constraint.pcf --report=synth_pnr_report.json
-	${Q}../tools/parse_nextpnr_stats.sh --brief synth_pnr_report.json
-	${Q}mv "$@.1" "$@"
-
-synth_ecp5.bit:synth_ecp5_out.config
-	${QUIET_ECPPACK}
-	${Q}ecppack --compress --freq 38.8 --input $< --bit $@
-
-synth_ecp5.dfu:synth_ecp5.bit
-	${QUIET_DFU_SUFFIX}
-	${Q}cp "$<" synth_ecp5.temp_dfu
-	@#From some testing, dfu-suffix does output errors to stderr so this should be fine
-	${Q}dfu-suffix --vid 1209 --pid 5af0 --add synth_ecp5.temp_dfu > /dev/null
-	${Q}mv synth_ecp5.temp_dfu "$@"
-
-upload_orangecrab:synth_ecp5.dfu
-	${QUIET_DFU_UTIL}
-	${Q}stdbuf -o0 dfu-util --download "$<" |stdbuf -o0 tr '\n' '\a' | stdbuf -o0 tr '\r' '\n' | grep Download --line-buffered | stdbuf -o0 tr '\n' '\r' |stdbuf -o0 tr '\a' '\n'
-
-nextpnr-gui: synth_ecp5.json
-	${QUIET_NEXTPNR}
-	${Q} nextpnr-ecp5 --seed ${NEXTPNR_SEED} --json $< ${NEXTPNR_ECP5_DEV} --package ${ECP5_PACKAGE} --speed 8 --lpf fpga_config/${FPGA_BOARD}/pin_constraint.pcf --gui
-
 external_ip/litedram_core_ecp5_phy.v:
 	${QUIET_DOWNLOAD}
 	${Q}../tools/gen_litedram.sh -q "$@"
 
-upload: upload_orangecrab
+#########################################
+##     SYNTHESIS  RECIPES
+
+SYNTHESIS_SOURCES ::= ${SOURCES} fpga_config/${FPGA_BOARD}/fpga_top.v ${SOC_SYNTHESIS_SOURCES} ${INCLUDES}
+
+#TODO: we are relying on yosys to trim the input program txt file and hope its enough for the whole program...
+${BUILD_FILES_PREFIX}synth_ecp5_${FPGA_BOARD}.json: ${SYNTHESIS_SOURCES} ${FPGA_BOOTCODE} simplified_ucode.txt
+	${QUIET_YOSYS}
+	${Q} yosys -q -p 'read_verilog -defer -noautowire -sv '"${SYNTHESIS_SOURCES}; attrmap -tocase keep -imap keep="true" keep=1 -imap keep="false" keep=0 -remove keep=0; synth_ecp5 -json \"$@\" -abc9 -top fpga_top"
+
+##########################################
+##     PLACE AND ROUTE RECIPES
+
+${BUILD_FILES_PREFIX}nextpnr_${BUILD_NAME}.bit:${BUILD_FILES_PREFIX}synth_${FPGA_BOARD}.json
+	${QUIET_NEXTPNR}
+	${Q}printf '\e[1;30mNotice: nextpnr rng seed is : %s\e[0m\n' "${FPGA_SEED}"
+	${Q} nextpnr-ecp5 --seed ${FPGA_SEED} --Werror -q --json $< --textcfg "$@_config_temp" ${NEXTPNR_ECP5_DEV} --package ${ECP5_PACKAGE} --speed ${ECP5_SPEED_GRADE} --lpf fpga_config/${FPGA_BOARD}/pin_constraint.pcf --report=${BUILD_FILES_PREFIX}nextpnr_report_${BUILD_NAME}.json
+	${Q}../tools/parse_nextpnr_stats.sh --brief ${BUILD_FILES_PREFIX}nextpnr_report_${BUILD_NAME}.json
+	${Q}mv "$@_config_temp" "$@_config" # nextpnr-ecp5 will still generate a file even if it fails breaking the assumptions of the build system.
+	${QUIET_ECPPACK}
+	${Q}ecppack --compress --freq 38.8 --input $@_config --bit $@
+
+nextpnr-gui: ${BUILD_FILES_PREFIX}synth_${FPGA_BOARD}.json
+	${QUIET_NEXTPNR}
+	${Q} nextpnr-ecp5 --seed ${FPGA_SEED} --json $< ${NEXTPNR_ECP5_DEV} --package ${ECP5_PACKAGE} --speed ${ECP5_SPEED_GRADE} --lpf fpga_config/${FPGA_BOARD}/pin_constraint.pcf --gui
+
+##########################################
+##     BITSTREAM MODIFICATION FOR/AND UPLOADING
+
+${BUILD_FILES_PREFIX}bitstream_${BUILD_NAME}.dfu:${BUILD_FILES_PREFIX}bitstream_${BUILD_NAME}.bit
+	${QUIET_DFU_SUFFIX}
+	${Q}cp "$<" "$<.tempdfu"
+	@#From some testing, dfu-suffix does output errors to stderr so this should be fine
+	${Q}dfu-suffix --vid 1209 --pid 5af0 --add "$<.tempdfu" > /dev/null
+	${Q}mv "$<.tempdfu" "$@"
+
+dfu_upload:${BUILD_FILES_PREFIX}bitstream_${BUILD_NAME}.dfu
+	${QUIET_DFU_UTIL}
+	${Q}stdbuf -o0 dfu-util --download "$<" |stdbuf -o0 tr '\n' '\a' | stdbuf -o0 tr '\r' '\n' | grep Download --line-buffered | stdbuf -o0 tr '\n' '\r' |stdbuf -o0 tr '\a' '\n'
+
+
+################################################################################
+####                                CLEAN-UP                                ####
+################################################################################
+
 
 .PHONY: clean
 clean:
 	$(call QUIET_CLEAN,system)
-	${Q}rm -rf ${SYSTEM_VVP} *.fst boot_code.txt boot_code.bin *memdump *memdumptxt obj_dir *json simplified_ucode.txt ${ECP5_TARGETS}
+	${Q}rm -rf ${SYSTEM_VVP} *.fst boot_code.txt boot_code.bin *memdump *memdumptxt obj_dir simplified_ucode.txt abc.history build

system/fpga_config/OrangeCrab_r0.2.1/config.mk

@@ -5,3 +5,27 @@ ECP5_DEVICE=25F
 #              85F: Create bitstream for the LFE5U-85F
 ECP5_PACKAGE=CSFBGA285
 # ECP5_PACKAGE: CSFBGA285: The one used in OrangeCrab
+
+FPGA_FILE_EXT=dfu
+
+#This is on the 8th postiion in the chip id, for example
+# LFE5U-25-7BG381I
+#          ^---------- this would be a 7 speed grade
+#
+# 6 is the slowest and 8 is the fastest
+ECP5_SPEED_GRADE=8
+
+
+########   End fo user configuration   ########
+
+SOC_SYNTHESIS_SOURCES=peripherals/I2C_driver.v peripherals/ascii_to_HD44780_driver.v peripherals/pcf8574_for_HD44780.v peripherals/Wishbone_IO_driver.v peripherals/Wishbone_memory_driver.v external_ip/litedram_core_ecp5_phy.v
+
+FPGA_BOOTCODE=../boot_code/bios.stxt
+
+upload: dfu_upload
+
+${BUILD_FILES_PREFIX}bitstream_${BUILD_NAME}.bit:${BUILD_FILES_PREFIX}nextpnr_${BUILD_NAME}.bit
+	${Q}cp "$^" "$@"
+
+${BUILD_FILES_PREFIX}synth_${FPGA_BOARD}.json:${BUILD_FILES_PREFIX}synth_ecp5_${FPGA_BOARD}.json
+	${Q}cp "$^" "$@"