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Small change from when I last worked on this and an update to the versions on the README

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(Tim) Efthimis Kritikos 2023-10-21 18:38:35 +01:00
parent 42c319d55d
commit 8d3b54b812
2 changed files with 4 additions and 4 deletions
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4
README.md
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@ -19,11 +19,11 @@ A CPU that aims to be binary compatible with the 8086 ISA, focused on optimisati
Both Verilator and Icarus Verilog can be used for simulation. You can select which one you want with the SIM variable on [common.mk](./common.mk) Both Verilator and Icarus Verilog can be used for simulation. You can select which one you want with the SIM variable on [common.mk](./common.mk)
Specifically this list shows the software needed and the versions used during development (other versions should work as well) Specifically this list shows the software needed and the versions used during development (other versions should work as well)
* Icarus Verilog : version 11.0 OR **(preferred)** Verilator : 5.008 * Icarus Verilog : version 12.0 OR **(preferred)** Verilator : 5.016
* bin86 : 0.16.21 * bin86 : 0.16.21
* GNU Make : 4.4.1 * GNU Make : 4.4.1
* xxd : 2022-01-14 * xxd : 2022-01-14
* POSIX coreutils : GNU coreutils 9.3 * POSIX coreutils : GNU coreutils 9.4
After that you can run `make` on the top level directory and it should build everything and start the simulation After that you can run `make` on the top level directory and it should build everything and start the simulation

4
system/biu.v
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@ -43,7 +43,7 @@ module BIU (
/* */ input clock, input reset /* */ input clock, input reset
/**************** OUTSIDE WORLD ****************/ /**************** OUTSIDE WORLD ****************/
/* */ ,output reg [19:0] external_address_bus /* */ ,output wire [19:0] external_address_bus
/* */ ,inout [15:0] external_data_bus,output reg read, output reg write,output reg BHE,output reg IOMEM /* */ ,inout [15:0] external_data_bus,output reg read, output reg write,output reg BHE,output reg IOMEM
/**************** OUTPUT TO DE ****************/ /**************** OUTPUT TO DE ****************/
@ -105,7 +105,7 @@ reg func;
reg [19:0]INSTRUCTION_ADDRESS; reg [19:0]INSTRUCTION_ADDRESS;
reg [19:0]DATA_ADDRESS; reg [19:0]DATA_ADDRESS;
assign external_address_bus= func? INSTRUCTION_ADDRESS : DATA_ADDRESS ; assign external_address_bus= func ? INSTRUCTION_ADDRESS : DATA_ADDRESS ;
always @(posedge clock) begin always @(posedge clock) begin
if ( jump_req_latch ) begin if ( jump_req_latch ) begin