diff --git a/README.md b/README.md
index ce1b197..8cd1117 100644
--- a/README.md
+++ b/README.md
@@ -19,11 +19,11 @@ A CPU that aims to be binary compatible with the 8086 ISA, focused on optimisati
 Both Verilator and Icarus Verilog can be used for simulation. You can select which one you want with the SIM variable on [common.mk](./common.mk)
 Specifically this list shows the software needed and the versions used during development (other versions should work as well)
 
-* Icarus Verilog : version 11.0  OR **(preferred)** Verilator : 5.008
+* Icarus Verilog : version 12.0  OR **(preferred)** Verilator : 5.016
 * bin86 : 0.16.21
 * GNU Make : 4.4.1
 * xxd : 2022-01-14
-* POSIX coreutils : GNU coreutils 9.3
+* POSIX coreutils : GNU coreutils 9.4
 
 After that you can run `make` on the top level directory and it should build everything and start the simulation
 
diff --git a/system/biu.v b/system/biu.v
index 8a10670..256d9fa 100644
--- a/system/biu.v
+++ b/system/biu.v
@@ -43,7 +43,7 @@ module BIU (
 	/*               */  input clock, input reset
 
 	/**************** OUTSIDE WORLD ****************/
-	/*               */ ,output reg [19:0] external_address_bus
+	/*               */ ,output wire [19:0] external_address_bus
 	/*               */ ,inout [15:0] external_data_bus,output reg read, output reg write,output reg BHE,output reg IOMEM
 
 	/**************** OUTPUT TO DE  ****************/
@@ -105,7 +105,7 @@ reg func;
 reg [19:0]INSTRUCTION_ADDRESS;
 reg [19:0]DATA_ADDRESS;
 
-assign external_address_bus= func? INSTRUCTION_ADDRESS : DATA_ADDRESS ;
+assign external_address_bus= func ? INSTRUCTION_ADDRESS : DATA_ADDRESS ;
 
 always @(posedge clock) begin
 	if ( jump_req_latch ) begin