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Changed slogan and cleaned up some small pieces of code

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(Tim) Efthimis Kritikos 2023-05-23 16:18:33 +01:00
parent 0bf00df07c
commit 79d598fc64
7 changed files with 13 additions and 13 deletions
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4
8086_documentation.md
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@ -12,7 +12,7 @@ Instructions vary from 1 to 6 bytes.
On some instructions: On some instructions:
* **S**-bit : An 8-bit 2's complement number. It can be extended to a 16-bit 2’s complement number internally depending on the W-bit * **S**-bit : An 8-bit 2's complement number. It can be extended to a 16-bit 2’s complement number internally depending on the W-bit
| S | W | Operation | | S | W | Operation |
| --- | --- | ----------------------------------------------------- | | --- | --- | ----------------------------------------------------- |
@ -30,7 +30,7 @@ No instruction has parts of its opcode past the first 2 bytes I.e. all bytes aft
The second byte of the instruction usually identifies the instruction's operands. The **MOD** (mode) field weather or not the operands is in memory or if both are registers. In some instructions like the immediate-to-memory type the **REG** field is used as an extension of the opcode. The function of **R/M** depends on how MOD. if MOD=11 (register-register mode) then **R/M** specifies the second Register, otherwise it specifies how the effective address in memory is calculated The second byte of the instruction usually identifies the instruction's operands. The **MOD** (mode) field weather or not the operands is in memory or if both are registers. In some instructions like the immediate-to-memory type the **REG** field is used as an extension of the opcode. The function of **R/M** depends on how MOD. if MOD=11 (register-register mode) then **R/M** specifies the second Register, otherwise it specifies how the effective address in memory is calculated
|R/M | Memory indirect with no displacement [ 0 0 ] | Memory indirect with 8 bit displacement [ 0 1 ] | Memory indirect with 16 bit displacement [ 1 0 ] | Register Mode [ 1 1 ] W = 0| Register Mode [ 1 1 ] W = 1 | |R/M | Memory indirect with no displacement [ 0 0 ] | Memory indirect with 8 bit displacement [ 0 1 ] | Memory indirect with 16 bit displacement [ 1 0 ] | Register Mode [ 1 1 ] W = 0| Register Mode [ 1 1 ] W = 1 |
|---- | ---------------------------------------- | ------------------------------------------- | -------------------------------------------- | --------------------------- | --------------------------- | |---- | ---------------------------------------- | ------------------------------------------- | -------------------------------------------- | --------------------------- | --------------------------- |
|000 | [BX] + [SI] | [BX] + [SI] + d8 | [BX] + [SI] + d16 | AL | AX | |000 | [BX] + [SI] | [BX] + [SI] + d8 | [BX] + [SI] + d16 | AL | AX |
|001 | [BX] + [DI] | [BX] + [DI] + d8 | [BX] + [DI] + d16 | CL | CX | |001 | [BX] + [DI] | [BX] + [DI] + d8 | [BX] + [DI] + d16 | CL | CX |
|010 | [BP] + [SI] | [BP] + [SI] + d8 | [BP] + [SI] + d16 | DL | DX | |010 | [BP] + [SI] | [BP] + [SI] + d8 | [BP] + [SI] + d16 | DL | DX |

2
README.md
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@ -1,7 +1,7 @@
<img width="186" height="70" style=" margin: 10px 0px 10px 10px;" alt="9086 logo" src="readme_files/9086_design1.svg"> <img width="186" height="70" style=" margin: 10px 0px 10px 10px;" alt="9086 logo" src="readme_files/9086_design1.svg">
A CPU that aims to be binary compatible with the 8086 and with as many optimisations as possible A CPU that aims to be binary compatible with the 8086 ISA, focused on optimisation and flexibility.
### Progress ### Progress

6
system/decoder.v
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@ -532,7 +532,7 @@ always @( FLAGS or CIR or SIMPLE_MICRO or seq_addr_input ) begin
DEPENDS_ON_PREVIOUS<=0; DEPENDS_ON_PREVIOUS<=0;
end end
11'b1111_011?_000:begin 11'b1111_011?_000:begin
/* TEST - Bitwise AND of immediate and registers/memmory affecting only flags */ /* TEST - Bitwise AND of immediate and registers/memory affecting only flags */
/* 1 1 1 1 0 1 1 W | MOD 0 0 0 R/M | < DISP-LO > | < DISP-HI > | DATA | DATA if W */ /* 1 1 1 1 0 1 1 W | MOD 0 0 0 R/M | < DISP-LO > | < DISP-HI > | DATA | DATA if W */
opcode_size=1; opcode_size=1;
Wbit=CIR[8:8]; Wbit=CIR[8:8];
@ -640,7 +640,7 @@ always @( FLAGS or CIR or SIMPLE_MICRO or seq_addr_input ) begin
memio_address_select=0; memio_address_select=0;
end end
11'b1100_1101_???:begin 11'b1100_1101_???:begin
/* INT - execute interrupt handler */ /* INT - Execute interrupt handler */
/* 1 1 0 0 1 1 0 1 | DATA |*/ /* 1 1 0 0 1 1 0 1 | DATA |*/
// [skipped] 1) push flags // [skipped] 1) push flags
// [skipped] 2) clear trap and interrupt enable flag // [skipped] 2) clear trap and interrupt enable flag
@ -658,7 +658,7 @@ always @( FLAGS or CIR or SIMPLE_MICRO or seq_addr_input ) begin
memio_address_select=0; memio_address_select=0;
end end
11'b1110_011?_???:begin 11'b1110_011?_???:begin
/* OUT - write AL or AX to a defined output port */ /* OUT - Write AL or AX to a defined output port */
/* | 1 1 1 0 0 1 1 W | DATA 8 | */ /* | 1 1 1 0 0 1 1 W | DATA 8 | */
memio_address_select=1; memio_address_select=1;
Wbit=CIR[8:8]; Wbit=CIR[8:8];

2
system/execute.v
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@ -25,7 +25,7 @@ module execute_unit (
/* STATE CONTROL */ ,output [`EXEC_STATE_BITS-1:0] _exec_state_, input [`EXEC_STATE_BITS-1:0] init_state /* STATE CONTROL */ ,output [`EXEC_STATE_BITS-1:0] _exec_state_, input [`EXEC_STATE_BITS-1:0] init_state
/* ALU CONTROL */ ,input [1:0] in_alu_sel1, input [1:0] in_alu_sel2, input [`ALU_OP_BITS-1:0] ALU_OP, output [15:0] _ALU_O_ /* ALU CONTROL */ ,input [1:0] in_alu_sel1, input [1:0] in_alu_sel2, input [`ALU_OP_BITS-1:0] ALU_OP, output [15:0] _ALU_O_
/* REGISTER DATA */ ,input [15:0] reg_read_port1_data ,input [15:0] reg_read_port2_data, output reg [3:0] reg_read_port1_addr, output reg use_exec_reg_addr, output reg reg_write_we /* REGISTER DATA */ ,input [15:0] reg_read_port1_data ,input [15:0] reg_read_port2_data, output reg [3:0] reg_read_port1_addr, output reg use_exec_reg_addr, output reg reg_write_we
/* FLAFS */ ,output reg [7:0] FLAGS /* FLAGS */ ,output reg [7:0] FLAGS
/* BIU */ ,output reg [15:0] BIU_ADDRESS_INPUT,output reg biu_write_request, output reg biu_read_request, input BIU_VALID_DATA, input [15:0] BIU_DATA, output reg biu_data_direction, output reg biu_jump_req /* BIU */ ,output reg [15:0] BIU_ADDRESS_INPUT,output reg biu_write_request, output reg biu_read_request, input BIU_VALID_DATA, input [15:0] BIU_DATA, output reg biu_data_direction, output reg biu_jump_req
); );

2
system/processor.v
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@ -93,7 +93,7 @@ execute_unit execute_unit (
/* STATE CONTROL */ ,exec_state, next_state /* STATE CONTROL */ ,exec_state, next_state
/* ALU CONTROL */ ,in_alu_sel1, in_alu_sel2, ALU_OP, ALU_O /* ALU CONTROL */ ,in_alu_sel1, in_alu_sel2, ALU_OP, ALU_O
/* REGISTER DATA */ ,reg_read_port1_data, reg_read_port2_data, EXEC_reg_read_port1_addr, use_exec_reg_addr, reg_write_we /* REGISTER DATA */ ,reg_read_port1_data, reg_read_port2_data, EXEC_reg_read_port1_addr, use_exec_reg_addr, reg_write_we
/* FLAFS */ ,EXEC_FLAGS /* FLAGS */ ,EXEC_FLAGS
/* BIU */ ,BIU_ADDRESS_INPUT, biu_write_request, biu_read_request, BIU_VALID_DATA, BIU_DATA, biu_data_direction, biu_jump_req /* BIU */ ,BIU_ADDRESS_INPUT, biu_write_request, biu_read_request, BIU_VALID_DATA, BIU_DATA, biu_data_direction, biu_jump_req
); );

8
system/testbench.v
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@ -77,7 +77,7 @@ module clock_gen (input enable, output reg clk);
parameter FREQ = 1000; // in HZ parameter FREQ = 1000; // in HZ
parameter PHASE = 0; // in degrees parameter PHASE = 0; // in degrees
parameter DUTY = 50; // in percentage parameter DUTY = 50; // in percentage
real clk_pd = 1.0/FREQ * 1000000000; // convert to ms real clk_pd = 1.0/FREQ * 1000000000; // convert to ms
real clk_on = DUTY/100.0 * clk_pd; real clk_on = DUTY/100.0 * clk_pd;
@ -97,7 +97,7 @@ initial begin
end end
// When clock is enabled, delay driving the clock to one in order // When clock is enabled, delay driving the clock to one in order
// to achieve the phase effect. start_dly is configured to the // to achieve the phase effect. start_dly is configured to the
// correct delay for the configured phase. When enable is 0, // correct delay for the configured phase. When enable is 0,
// allow enough time to complete the current clock period // allow enough time to complete the current clock period
always @ (posedge enable or negedge enable) begin always @ (posedge enable or negedge enable) begin
@ -105,7 +105,7 @@ always @ (posedge enable or negedge enable) begin
#(start_dly) start_clk = 1; #(start_dly) start_clk = 1;
end else begin end else begin
#(start_dly) start_clk = 0; #(start_dly) start_clk = 0;
end end
end end
// Achieve duty cycle by a skewed clock on/off time and let this // Achieve duty cycle by a skewed clock on/off time and let this
@ -121,5 +121,5 @@ always @(posedge start_clk) begin
clk = 0; clk = 0;
end end
end end
endmodule endmodule

2
system/ucode.txt
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@ -74,7 +74,7 @@
// POP // POP
// mas|wbo|krs|rr2 |imd|rr1 |a1f|a1o|a12|a11|rwa |nxs|Nxt M | // mas|wbo|krs|rr2 |imd|rr1 |a1f|a1o|a12|a11|rwa |nxs|Nxt M |
@00a __0__00_100_0000_110_xxxx_011_011__00__11_xxxx_011_001011 // ALU_1: 0 ALU_2: PARAM2 ([SP]) ALU_OP:ADD ALU_out: REG @00a __0__00_100_0000_110_xxxx_011_011__00__11_xxxx_011_001011 // ALU_1: 0 ALU_2: PARAM2 ([SP]) ALU_OP:ADD ALU_out: REG
@00b __0__00_000_1100_011_0000_000_011__01__00_1100_000_000000 // ALU_1: PARAM1 (2) ALU_2: SP ALU_OP:ADD ALU_out: SP @00b __0__00_000_1100_011_0000_000_011__01__00_1100_000_000000 // ALU_1: PARAM1 (2) ALU_2: SP ALU_OP:ADD ALU_out: SP
// PUSH // PUSH
// mas|wbo|krs|rr2 |imd|rr1 |a1f|a1o|a12|a11|rwa |nxs|Nxt M | // mas|wbo|krs|rr2 |imd|rr1 |a1f|a1o|a12|a11|rwa |nxs|Nxt M |