From 79d598fc6469360d3fe3503925ebef92b33fee31 Mon Sep 17 00:00:00 2001 From: "(Tim) Efthimis Kritikos" Date: Tue, 23 May 2023 16:18:33 +0100 Subject: [PATCH] Changed slogan and cleaned up some small pieces of code --- 8086_documentation.md | 4 ++-- README.md | 2 +- system/decoder.v | 6 +++--- system/execute.v | 2 +- system/processor.v | 2 +- system/testbench.v | 8 ++++---- system/ucode.txt | 2 +- 7 files changed, 13 insertions(+), 13 deletions(-) diff --git a/8086_documentation.md b/8086_documentation.md index 1165ce7..6b577d8 100644 --- a/8086_documentation.md +++ b/8086_documentation.md @@ -12,7 +12,7 @@ Instructions vary from 1 to 6 bytes. On some instructions: -* **S**-bit : An 8-bit 2's complement number. It can be extended to a 16-bit 2’s complement number internally depending on the W-bit +* **S**-bit : An 8-bit 2's complement number. It can be extended to a 16-bit 2’s complement number internally depending on the W-bit | S | W | Operation | | --- | --- | ----------------------------------------------------- | @@ -30,7 +30,7 @@ No instruction has parts of its opcode past the first 2 bytes I.e. all bytes aft The second byte of the instruction usually identifies the instruction's operands. The **MOD** (mode) field weather or not the operands is in memory or if both are registers. In some instructions like the immediate-to-memory type the **REG** field is used as an extension of the opcode. The function of **R/M** depends on how MOD. if MOD=11 (register-register mode) then **R/M** specifies the second Register, otherwise it specifies how the effective address in memory is calculated |R/M | Memory indirect with no displacement [ 0 0 ] | Memory indirect with 8 bit displacement [ 0 1 ] | Memory indirect with 16 bit displacement [ 1 0 ] | Register Mode [ 1 1 ] W = 0| Register Mode [ 1 1 ] W = 1 | -|---- | ---------------------------------------- | ------------------------------------------- | -------------------------------------------- | --------------------------- | --------------------------- | +|---- | ---------------------------------------- | ------------------------------------------- | -------------------------------------------- | --------------------------- | --------------------------- | |000 | [BX] + [SI] | [BX] + [SI] + d8 | [BX] + [SI] + d16 | AL | AX | |001 | [BX] + [DI] | [BX] + [DI] + d8 | [BX] + [DI] + d16 | CL | CX | |010 | [BP] + [SI] | [BP] + [SI] + d8 | [BP] + [SI] + d16 | DL | DX | diff --git a/README.md b/README.md index aedac20..ce1b197 100644 --- a/README.md +++ b/README.md @@ -1,7 +1,7 @@ 9086 logo -A CPU that aims to be binary compatible with the 8086 and with as many optimisations as possible +A CPU that aims to be binary compatible with the 8086 ISA, focused on optimisation and flexibility. ### Progress diff --git a/system/decoder.v b/system/decoder.v index c4332b1..6facfe1 100644 --- a/system/decoder.v +++ b/system/decoder.v @@ -532,7 +532,7 @@ always @( FLAGS or CIR or SIMPLE_MICRO or seq_addr_input ) begin DEPENDS_ON_PREVIOUS<=0; end 11'b1111_011?_000:begin - /* TEST - Bitwise AND of immediate and registers/memmory affecting only flags */ + /* TEST - Bitwise AND of immediate and registers/memory affecting only flags */ /* 1 1 1 1 0 1 1 W | MOD 0 0 0 R/M | < DISP-LO > | < DISP-HI > | DATA | DATA if W */ opcode_size=1; Wbit=CIR[8:8]; @@ -640,7 +640,7 @@ always @( FLAGS or CIR or SIMPLE_MICRO or seq_addr_input ) begin memio_address_select=0; end 11'b1100_1101_???:begin - /* INT - execute interrupt handler */ + /* INT - Execute interrupt handler */ /* 1 1 0 0 1 1 0 1 | DATA |*/ // [skipped] 1) push flags // [skipped] 2) clear trap and interrupt enable flag @@ -658,7 +658,7 @@ always @( FLAGS or CIR or SIMPLE_MICRO or seq_addr_input ) begin memio_address_select=0; end 11'b1110_011?_???:begin - /* OUT - write AL or AX to a defined output port */ + /* OUT - Write AL or AX to a defined output port */ /* | 1 1 1 0 0 1 1 W | DATA 8 | */ memio_address_select=1; Wbit=CIR[8:8]; diff --git a/system/execute.v b/system/execute.v index a75eb9f..2a6aa1e 100644 --- a/system/execute.v +++ b/system/execute.v @@ -25,7 +25,7 @@ module execute_unit ( /* STATE CONTROL */ ,output [`EXEC_STATE_BITS-1:0] _exec_state_, input [`EXEC_STATE_BITS-1:0] init_state /* ALU CONTROL */ ,input [1:0] in_alu_sel1, input [1:0] in_alu_sel2, input [`ALU_OP_BITS-1:0] ALU_OP, output [15:0] _ALU_O_ /* REGISTER DATA */ ,input [15:0] reg_read_port1_data ,input [15:0] reg_read_port2_data, output reg [3:0] reg_read_port1_addr, output reg use_exec_reg_addr, output reg reg_write_we - /* FLAFS */ ,output reg [7:0] FLAGS + /* FLAGS */ ,output reg [7:0] FLAGS /* BIU */ ,output reg [15:0] BIU_ADDRESS_INPUT,output reg biu_write_request, output reg biu_read_request, input BIU_VALID_DATA, input [15:0] BIU_DATA, output reg biu_data_direction, output reg biu_jump_req ); diff --git a/system/processor.v b/system/processor.v index 96e8f39..39953c2 100644 --- a/system/processor.v +++ b/system/processor.v @@ -93,7 +93,7 @@ execute_unit execute_unit ( /* STATE CONTROL */ ,exec_state, next_state /* ALU CONTROL */ ,in_alu_sel1, in_alu_sel2, ALU_OP, ALU_O /* REGISTER DATA */ ,reg_read_port1_data, reg_read_port2_data, EXEC_reg_read_port1_addr, use_exec_reg_addr, reg_write_we - /* FLAFS */ ,EXEC_FLAGS + /* FLAGS */ ,EXEC_FLAGS /* BIU */ ,BIU_ADDRESS_INPUT, biu_write_request, biu_read_request, BIU_VALID_DATA, BIU_DATA, biu_data_direction, biu_jump_req ); diff --git a/system/testbench.v b/system/testbench.v index 12ba661..480398b 100644 --- a/system/testbench.v +++ b/system/testbench.v @@ -77,7 +77,7 @@ module clock_gen (input enable, output reg clk); parameter FREQ = 1000; // in HZ parameter PHASE = 0; // in degrees -parameter DUTY = 50; // in percentage +parameter DUTY = 50; // in percentage real clk_pd = 1.0/FREQ * 1000000000; // convert to ms real clk_on = DUTY/100.0 * clk_pd; @@ -97,7 +97,7 @@ initial begin end // When clock is enabled, delay driving the clock to one in order -// to achieve the phase effect. start_dly is configured to the +// to achieve the phase effect. start_dly is configured to the // correct delay for the configured phase. When enable is 0, // allow enough time to complete the current clock period always @ (posedge enable or negedge enable) begin @@ -105,7 +105,7 @@ always @ (posedge enable or negedge enable) begin #(start_dly) start_clk = 1; end else begin #(start_dly) start_clk = 0; - end + end end // Achieve duty cycle by a skewed clock on/off time and let this @@ -121,5 +121,5 @@ always @(posedge start_clk) begin clk = 0; end -end +end endmodule diff --git a/system/ucode.txt b/system/ucode.txt index 23328bc..c0cabe8 100644 --- a/system/ucode.txt +++ b/system/ucode.txt @@ -74,7 +74,7 @@ // POP // mas|wbo|krs|rr2 |imd|rr1 |a1f|a1o|a12|a11|rwa |nxs|Nxt M | @00a __0__00_100_0000_110_xxxx_011_011__00__11_xxxx_011_001011 // ALU_1: 0 ALU_2: PARAM2 ([SP]) ALU_OP:ADD ALU_out: REG -@00b __0__00_000_1100_011_0000_000_011__01__00_1100_000_000000 // ALU_1: PARAM1 (2) ALU_2: SP ALU_OP:ADD ALU_out: SP +@00b __0__00_000_1100_011_0000_000_011__01__00_1100_000_000000 // ALU_1: PARAM1 (2) ALU_2: SP ALU_OP:ADD ALU_out: SP // PUSH // mas|wbo|krs|rr2 |imd|rr1 |a1f|a1o|a12|a11|rwa |nxs|Nxt M |