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Removed deprecated BIU_NEXT_POSITION

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(Tim) Efthimis Kritikos 2023-05-10 08:53:19 +01:00
parent e4ef199b83
commit 7724e5f383
2 changed files with 13 additions and 22 deletions
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21
system/biu.v
View File

@ -40,7 +40,7 @@
module BIU ( module BIU (
/*outside world*/ input clock, input reset, output reg [19:0] external_address_bus, /*outside world*/ input clock, input reset, output reg [19:0] external_address_bus,
/* */ inout [15:0] external_data_bus,output reg read, output reg write,output reg BHE,output reg IOMEM, /* */ inout [15:0] external_data_bus,output reg read, output reg write,output reg BHE,output reg IOMEM,
/* internal */ output reg [31:0] INSTRUCTION, output reg VALID_INSTRUCTION, output reg [15:0] INSTRUCTION_LOCATION, input [1:0] NEXT_POSITION, /* internal */ output reg [31:0] INSTRUCTION, output reg VALID_INSTRUCTION, output reg [15:0] INSTRUCTION_LOCATION, input jump_req,
/* */ input[15:0] ADDRESS_INPUT, inout [15:0] DATA, input write_request, input read_request, input Wbit, output reg VALID_DATA, input MEM_OR_IO, /* */ input[15:0] ADDRESS_INPUT, inout [15:0] DATA, input write_request, input read_request, input Wbit, output reg VALID_DATA, input MEM_OR_IO,
/* */ input [`PROC_STATE_BITS-1:0] proc_state, input SIMPLE_MICRO /* */ input [`PROC_STATE_BITS-1:0] proc_state, input SIMPLE_MICRO
); );
@ -70,7 +70,7 @@ always @(posedge reset) begin
biu_state <= `BIU_RESET; biu_state <= `BIU_RESET;
end end
reg jump_req; reg jump_req_latch;
reg func; reg func;
reg [19:0]INSTRUCTION_ADDRESS; reg [19:0]INSTRUCTION_ADDRESS;
@ -81,7 +81,7 @@ assign external_address_bus= func? INSTRUCTION_ADDRESS : DATA_ADDRESS ;
/* Read into the FIFO */ /* Read into the FIFO */
always @(posedge clock) begin always @(posedge clock) begin
if ( jump_req ) begin if ( jump_req_latch ) begin
/* verilator lint_off BLKSEQ */ /* verilator lint_off BLKSEQ */
FIFO_start = 0; FIFO_start = 0;
/* verilator lint_on BLKSEQ */ /* verilator lint_on BLKSEQ */
@ -89,7 +89,7 @@ always @(posedge clock) begin
INSTRUCTION_ADDRESS <= { 4'b0 , ADDRESS_INPUT }; INSTRUCTION_ADDRESS <= { 4'b0 , ADDRESS_INPUT };
INSTRUCTION_LOCATION <= ADDRESS_INPUT; INSTRUCTION_LOCATION <= ADDRESS_INPUT;
func <= 1; func <= 1;
jump_req <= 0; jump_req_latch <= 0;
if (biu_state==`BIU_READ) if (biu_state==`BIU_READ)
biu_state <= `BIU_NEXT_ACTION; biu_state <= `BIU_NEXT_ACTION;
end else begin end else begin
@ -330,18 +330,9 @@ always @( negedge SIMPLE_MICRO ) begin
was_simple <= 1; was_simple <= 1;
end end
always @( NEXT_POSITION ) begin always @( posedge jump_req ) begin
case(NEXT_POSITION) jump_req_latch <= 1;
2'b00:begin end /* no action */
2'b01:begin /* Next instruction */
end
2'b10:begin /* Jump to specific location based on register */
jump_req <= 1;
VALID_INSTRUCTION <= 0; VALID_INSTRUCTION <= 0;
end
2'b11:begin /* Jump to absolute location */
end
endcase
end end
endmodule endmodule

12
system/processor.v
View File

@ -37,7 +37,7 @@ reg [`PROC_STATE_BITS-1:0] state;
/*############ Bus Interface Unit ############################################### */ /*############ Bus Interface Unit ############################################### */
wire [31:0] INSTRUCTION; wire [31:0] INSTRUCTION;
reg [1:0] BIU_NEXT_POSITION; reg jump_req;
wire VALID_INSTRUCTION; wire VALID_INSTRUCTION;
wire [15:0] INSTRUCTION_LOCATION; wire [15:0] INSTRUCTION_LOCATION;
reg [15:0] BIU_ADDRESS_INPUT; reg [15:0] BIU_ADDRESS_INPUT;
@ -49,7 +49,7 @@ wire BIU_VALID_DATA;
BIU BIU( BIU BIU(
clock,reset,external_address_bus,external_data_bus,read,write,BHE,IOMEM, clock,reset,external_address_bus,external_data_bus,read,write,BHE,IOMEM,
INSTRUCTION,VALID_INSTRUCTION,INSTRUCTION_LOCATION,BIU_NEXT_POSITION,BIU_ADDRESS_INPUT,BIU_DATA,biu_write_request,biu_read_request,Wbit,BIU_VALID_DATA,MEM_OR_IO, INSTRUCTION,VALID_INSTRUCTION,INSTRUCTION_LOCATION,jump_req,BIU_ADDRESS_INPUT,BIU_DATA,biu_write_request,biu_read_request,Wbit,BIU_VALID_DATA,MEM_OR_IO,
state,SIMPLE_MICRO state,SIMPLE_MICRO
); );
assign BIU_DATA= biu_data_direction ? 16'hz : (memio_address_select?reg_read_port1_data:ALU_1O); assign BIU_DATA= biu_data_direction ? 16'hz : (memio_address_select?reg_read_port1_data:ALU_1O);
@ -221,7 +221,7 @@ reg [23:0] INSTRUCTION_BUFFER;
always @(posedge clock) begin always @(posedge clock) begin
case(state) case(state)
`PROC_RESET:begin `PROC_RESET:begin
BIU_NEXT_POSITION <= 0; jump_req <= 0;
ucode_seq_addr <= `UCODE_NO_INSTRUCTION; ucode_seq_addr <= `UCODE_NO_INSTRUCTION;
HALT <= 0; HALT <= 0;
ERROR <= `ERR_NO_ERROR; ERROR <= `ERR_NO_ERROR;
@ -284,11 +284,11 @@ always @(posedge clock) begin
ucode_seq_addr <= ucode_seq_addr_entry; ucode_seq_addr <= ucode_seq_addr_entry;
SIMPLE_MICRO <= 1; SIMPLE_MICRO <= 1;
/*keep state the same and rerun decode this time with all the data from the microcode rom*/ /*keep state the same and rerun decode this time with all the data from the microcode rom*/
BIU_NEXT_POSITION <= 2'b00; jump_req <= 0;
end else begin end else begin
state <= next_state; state <= next_state;
if ( SIMPLE_MICRO == 0 ) begin if ( SIMPLE_MICRO == 0 ) begin
BIU_NEXT_POSITION <= 2'b00; jump_req <= 0;
end end
end end
end end
@ -477,7 +477,7 @@ always @(posedge clock) begin
end end
3'b101:begin /* Program Counter*/ 3'b101:begin /* Program Counter*/
BIU_ADDRESS_INPUT <= ALU_1O[15:0]; BIU_ADDRESS_INPUT <= ALU_1O[15:0];
BIU_NEXT_POSITION <= 2'b10; jump_req <= 1;
instruction_size_init <= 1; instruction_size_init <= 1;
if (ucode_seq_addr==`UCODE_NO_INSTRUCTION) if (ucode_seq_addr==`UCODE_NO_INSTRUCTION)
state <= `PROC_DE_STATE_ENTRY; state <= `PROC_DE_STATE_ENTRY;