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Fixed bug that prevented Icarus Verilog from simulating correctly

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(Tim) Efthimis Kritikos 2023-05-11 19:55:47 +01:00
parent 539fb8416b
commit 7151d5634f
1 changed files with 1 additions and 1 deletions
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system/biu.v
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@ -284,7 +284,7 @@ InstrSize InstrSize({INSTRUCTION[31:24],INSTRUCTION[21:19]},Isize);
wire [2:0] fifoIsize; wire [2:0] fifoIsize;
wire Isit1; wire Isit1;
`ifdef EARLY_VALID_INSTRUCTION `ifdef EARLY_VALID_INSTRUCTION
InstrSize fifoInstrSize({INPUT_FIFO[FIFO_start][7:0],INPUT_FIFO[FIFO_start+1][5:3]},fifoIsize); InstrSize fifoInstrSize({INPUT_FIFO[FIFO_start][7:0],INPUT_FIFO[FIFO_start+4'd1][5:3]},fifoIsize);
Is1 Is1(INPUT_FIFO[FIFO_start][7:0],Isit1); Is1 Is1(INPUT_FIFO[FIFO_start][7:0],Isit1);
`endif `endif