From 7151d5634f9092c34cad3ca2c54118846da5f379 Mon Sep 17 00:00:00 2001
From: "(Tim) Efthimis Kritikos" <efkf@firemail.cc>
Date: Thu, 11 May 2023 19:55:47 +0100
Subject: [PATCH] Fixed bug that prevented Icarus Verilog from simulating
 correctly

---
 system/biu.v | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/system/biu.v b/system/biu.v
index ceda3c5..7e11619 100644
--- a/system/biu.v
+++ b/system/biu.v
@@ -284,7 +284,7 @@ InstrSize InstrSize({INSTRUCTION[31:24],INSTRUCTION[21:19]},Isize);
 wire [2:0] fifoIsize;
 wire Isit1;
 `ifdef EARLY_VALID_INSTRUCTION
-InstrSize fifoInstrSize({INPUT_FIFO[FIFO_start][7:0],INPUT_FIFO[FIFO_start+1][5:3]},fifoIsize);
+InstrSize fifoInstrSize({INPUT_FIFO[FIFO_start][7:0],INPUT_FIFO[FIFO_start+4'd1][5:3]},fifoIsize);
 Is1 Is1(INPUT_FIFO[FIFO_start][7:0],Isit1);
 `endif