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Properly added fpga_top.v stuff in the build system and fixed some syntax errors

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This commit is contained in:
(Tim) Efthimis Kritikos 2023-11-02 22:00:07 +00:00
parent 43f3e16ca4
commit 601397b7f0
2 changed files with 13 additions and 10 deletions
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6
system/Makefile
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@ -15,7 +15,7 @@
# You should have received a copy of the GNU General Public License
# along with this program. If not, see <http://www.gnu.org/licenses/>.
#
TOP_LEVEL_SOURCE=system.v
TOP_LEVEL_SOURCE=system.v #TODO I really don't like this variable and its name
SOURCES=processor.v memory.v registers.v alu.v decoder.v general.v biu.v execute.v
EVENT_SIM_TESTBENCH=testbench.v
VERILATOR_TESTBENCH=testbench.cpp
@ -67,9 +67,9 @@ endif
ECP5_TARGETS=synth_ecp5.json synth_ecp5_out.config synth_ecp5.bit synth_ecp5.dfu fpga_config/${FPGA_BOARD}/fpga_top.v
ECP5_TARGETS+=abc.history # created from yosys
synth_ecp5.json: ${SOURCES} ${TOP_LEVEL_SOURCE} ${INCLUDES} boot_code.txt
synth_ecp5.json: ${SOURCES} ${TOP_LEVEL_SOURCE} fpga_config/${FPGA_BOARD}/fpga_top.v ${INCLUDES} boot_code.txt
${QUIET_YOSYS}
${Q} yosys -q -p 'read -sv '"${SOURCES} ${TOP_LEVEL_SOURCE} ; synth_ecp5 -json $@"
${Q} yosys -q -p 'read -sv '"${SOURCES} ${TOP_LEVEL_SOURCE} fpga_config/${FPGA_BOARD}/fpga_top.v ; synth_ecp5 -json $@"
synth_ecp5_out.config:synth_ecp5.json
${QUIET_NEXTPNR}

17
system/fpga_config/OrangeCrab_r0.2.1/fpga_top.v
View File

@ -22,19 +22,20 @@
module fpga_top(
input clk48,
input user_button;
output reset_n;
input user_button,
output reset_n,
output reg rgb_led0_r;
output reg rgb_led0_g;
output reg rgb_led0_b;
output reg rgb_led0_r,
output reg rgb_led0_g,
output reg rgb_led0_b,
);
wire HALT,[`ERROR_BITS-1:0]ERROR;
wire HALT;
wire [`ERROR_BITS-1:0]ERROR;
system system(
/* MISC */ clk48,user_button,HALT,ERROR
/* MEMORY / IO */ ,address_bus,data_bus,rd,wr,BHE,IOMEM
)
);
always @(HALT or ERROR or user_button) begin
if (HALT==0) begin
@ -53,3 +54,5 @@ always @(HALT or ERROR or user_button) begin
rgb_led_b=1;
end
end
endmodule