diff --git a/system/Makefile b/system/Makefile index 3a08d75..83cf4e7 100644 --- a/system/Makefile +++ b/system/Makefile @@ -15,7 +15,7 @@ # You should have received a copy of the GNU General Public License # along with this program. If not, see . # -TOP_LEVEL_SOURCE=system.v +TOP_LEVEL_SOURCE=system.v #TODO I really don't like this variable and its name SOURCES=processor.v memory.v registers.v alu.v decoder.v general.v biu.v execute.v EVENT_SIM_TESTBENCH=testbench.v VERILATOR_TESTBENCH=testbench.cpp @@ -67,9 +67,9 @@ endif ECP5_TARGETS=synth_ecp5.json synth_ecp5_out.config synth_ecp5.bit synth_ecp5.dfu fpga_config/${FPGA_BOARD}/fpga_top.v ECP5_TARGETS+=abc.history # created from yosys -synth_ecp5.json: ${SOURCES} ${TOP_LEVEL_SOURCE} ${INCLUDES} boot_code.txt +synth_ecp5.json: ${SOURCES} ${TOP_LEVEL_SOURCE} fpga_config/${FPGA_BOARD}/fpga_top.v ${INCLUDES} boot_code.txt ${QUIET_YOSYS} - ${Q} yosys -q -p 'read -sv '"${SOURCES} ${TOP_LEVEL_SOURCE} ; synth_ecp5 -json $@" + ${Q} yosys -q -p 'read -sv '"${SOURCES} ${TOP_LEVEL_SOURCE} fpga_config/${FPGA_BOARD}/fpga_top.v ; synth_ecp5 -json $@" synth_ecp5_out.config:synth_ecp5.json ${QUIET_NEXTPNR} diff --git a/system/fpga_config/OrangeCrab_r0.2.1/fpga_top.v b/system/fpga_config/OrangeCrab_r0.2.1/fpga_top.v index 52fdfb8..4a721f2 100644 --- a/system/fpga_config/OrangeCrab_r0.2.1/fpga_top.v +++ b/system/fpga_config/OrangeCrab_r0.2.1/fpga_top.v @@ -22,19 +22,20 @@ module fpga_top( input clk48, - input user_button; - output reset_n; + input user_button, + output reset_n, - output reg rgb_led0_r; - output reg rgb_led0_g; - output reg rgb_led0_b; + output reg rgb_led0_r, + output reg rgb_led0_g, + output reg rgb_led0_b, ); -wire HALT,[`ERROR_BITS-1:0]ERROR; +wire HALT; +wire [`ERROR_BITS-1:0]ERROR; system system( /* MISC */ clk48,user_button,HALT,ERROR /* MEMORY / IO */ ,address_bus,data_bus,rd,wr,BHE,IOMEM -) +); always @(HALT or ERROR or user_button) begin if (HALT==0) begin @@ -53,3 +54,5 @@ always @(HALT or ERROR or user_button) begin rgb_led_b=1; end end + +endmodule