Added support to the build system for synthesising, place and routing, serialising and uploading the design to a Lattice ECP5 OrangeCrab FPGA

2023-11-02 00:29:14 +00:00 · 2023-11-02 00:29:14 +00:00 · 5feee9de57
commit 5feee9de57
parent 85512d5ace
10 changed files with 385 additions and 27 deletions
--- a/.gitignore
+++ b/.gitignore
@ -6,6 +6,10 @@
 *.swp
 *.memdump
 *.json
+*.dfu
+*.bit
+abc.history
+system/synth_ecp5_out.config
 boot_code/*.bin
 boot_code/*.txt
 system/boot_code.bin
--- a/3
+++ b/3
@ -47,3 +47,6 @@ ${VERILATOR_BIN}:
 clean:
 	${Q}make ${MAKEOPTS} -C system clean
 	${Q}make ${MAKEOPTS} -C boot_code clean
+
+upload:
+	make -C system upload
--- a/README.md
+++ b/README.md
@ -32,7 +32,13 @@ After that you can run `make` on the top level directory and it should build eve
 <img width="700" style=" margin: 10px 0px 10px 10px;" alt="9086 logo" src="readme_files/9086_overview.svg">

 ### License
-All parts of this project are licensed under the GNU General Public License version 3 or later
+All parts of this project and files in this repository are licensed under the GNU General Public License version 3 or later
+
+Efthymios Kritikos is the copyright owner for all files except the following:
+
+|    File                                                 | Copyright owner | Original license |
+| :-----------------------------------------------------: | :-------------: | :--------------: |
+| system/fpga_config/OrangeCrab_r0.2.1/pin_constraint.pcf |   Greg Davill   |       MIT        |

 ### Version names
 The version name consist of three numbers:
--- a/common.mk
+++ b/common.mk
@ -1,24 +1,50 @@
 .PRECIOUS:${BOOT_CODE}

+########## BUILD OPTIONS ##########
+
 QUIET=1
 # QUIET: 1=clean, non-verbose output
 #        2=normal make output

+####### SIMULATION OPTIONS ########
+
 SIM=VERILATOR
 # SIM: VERILATOR: use Verilator
 #      ICARUS: use Icarus Verilog

 NUMACTL=#numactl -m 0 -C 0,1 --

+######## SYNTHESIS OPTIONS ########
+
+FPGA_BOARD=OrangeCrab_r0.2.1
+# BOARD: the options are the directories in system/fpga_config/.
+#        Select the one you have
+
+#### ECP5 specific ####
+ECP5_DEVICE=25F
+# ECP5_DEVICE: 25F: Create bitstream for the LFE5U-25F
+#              85F: Create bitstream for the LFE5U-85F
+ECP5_PACKAGE=CSFBGA285
+# ECP5_PACKAGE: CSFBGA285: The one used in OrangeCrab
+
 VERSION="v0.2.0"
 COMMIT=$(shell git log --pretty=format:'%H' -1 |cat)

 ifeq "${QUIET}" "1"
-       QUIET_AS		= @echo   '  AS        '$@;
-       QUIET_CC		= @echo   '  CC        '$@;
-       QUIET_VVP	= @echo   '  VVP       '$@;
-       QUIET_IVERILOG	= @echo   '  IVERILOG  '$@;
-       QUIET_VERILATOR	= @echo   '  VERILATOR '$@;
+       QUIET_AS		= @echo   '  AS         '$@;
+
+       QUIET_VVP	= @echo   '  VVP        '$@;
+       QUIET_IVERILOG	= @echo   '  IVERILOG   '$@;
+
+       QUIET_VERILATOR	= @echo   '  VERILATOR  '$@;
+       QUIET_CC		= @echo   '  CC         '$@;
+
+       QUIET_YOSYS	= @echo   '  YOSYS      '$@;
+       QUIET_NEXTPNR	= @echo   '  NEXTPNR    '$@;
+       QUIET_ECPPACK	= @echo   '  ECPPACK    '$@;
+       QUIET_DFU_SUFFIX	= @echo   '  DFU-SUFFIX '$@;
+       QUIET_DFU_UTIL	= @echo   '  DFU-UTIL   '$<;
+
       QUIET_CLEAN	= @printf '  CLEAN   %s\n' $1;
       QUIET_VERILATOR_RUN = @printf '  %s  %s\n' $1 $2;
       Q = @
--- a/system/Makefile
+++ b/system/Makefile
@ -55,7 +55,44 @@ ${VERILATOR_BIN}.mk: ${VERILATOR_TESTBENCH} ${TOP_LEVEL_SOURCE} ${SOURCES} ${INC
 	${QUIET_VERILATOR}
 	${Q}verilator -DCALCULATE_IPC -DOTUPUT_JSON_STATISTICS ${VERILATOR_OPTS} $^

+# Synthesis and bitstream creation for ECP5
+ifeq "${ECP5_DEVICE}" "25F"
+NEXTPNR_ECP5_DEV=--25k
+else ifeq "${ECP5_DEVICE}" "85F"
+NEXTPNR_ECP5_DEV=--85k
+else
+$(error invalid ECP5 device ${ECP5_DEVICE})
+endif
+
+ECP5_TARGETS=synth_ecp5.json synth_ecp5_out.config synth_ecp5.bit synth_ecp5.dfu
+ECP5_TARGETS+=abc.history # created from yosys
+
+synth_ecp5.json: ${SOURCES} ${TOP_LEVEL_SOURCE} ${INCLUDES} boot_code.txt
+	${QUIET_YOSYS}
+	${Q} yosys -q -p 'read -sv '"${SOURCES} ${TOP_LEVEL_SOURCE} ; synth_ecp5 -json $@"
+
+synth_ecp5_out.config:synth_ecp5.json
+	${QUIET_NEXTPNR}
+	${Q} nextpnr-ecp5 --Werror -q --json $< --textcfg $@ ${NEXTPNR_ECP5_DEV} --package ${ECP5_PACKAGE} --lpf fpga_config/${FPGA_BOARD}/pin_constraint.pcf
+
+synth_ecp5.bit:synth_ecp5_out.config
+	${QUIET_ECPPACK}
+	${Q}ecppack --compress --freq 38.8 --input $< --bit $@
+
+synth_ecp5.dfu:synth_ecp5.bit
+	${QUIET_DFU_SUFFIX}
+	${Q}cp "$<" synth_ecp5.temp_dfu
+	@#From some testing, dfu-suffix does output errors to stderr so this should be fine
+	${Q}dfu-suffix --vid 1209 --pid 5af0 --add synth_ecp5.temp_dfu > /dev/null
+	${Q}mv synth_ecp5.temp_dfu "$@"
+
+upload_orangecrab:synth_ecp5.dfu
+	${QUIET_DFU_UTIL}
+	${Q}stdbuf -o0 dfu-util --download "$<" |stdbuf -o0 tr '\n' '\a' | stdbuf -o0 tr '\r' '\n' | grep Download --line-buffered | stdbuf -o0 tr '\n' '\r' |stdbuf -o0 tr '\a' '\n'
+
+upload: upload_orangecrab
+
 .PHONY: clean
 clean:
 	$(call QUIET_CLEAN,system)
-	${Q}rm -rf ${SYSTEM_VVP} *.fst boot_code.txt boot_code.bin *memdump *memdumptxt obj_dir *json
+	${Q}rm -rf ${SYSTEM_VVP} *.fst boot_code.txt boot_code.bin *memdump *memdumptxt obj_dir *json  ${ECP5_TARGETS}
--- a/system/decoder.v
+++ b/system/decoder.v
@ -224,6 +224,7 @@ module microcode(
 );

 initial begin
+`ifndef YOSYS
 	string ucode_path;
 	if($value$plusargs("MICROCODE=%s",ucode_path))begin
 		$readmemb(ucode_path,ucode_rom,0,`UCODE_SIZE-1);
@ -231,6 +232,10 @@ initial begin
 		$display("Please supply microcode rom file as a runtime vvp argument +MICROCODE=<path>");
 		$finish;
 	end
+`else
+	//TODO: don't have it hard coded
+	$readmemb("ucode.txt",ucode_rom,0,`UCODE_SIZE-1);
+`endif
 end

 reg [`UCODE_DATA_BITS-1:0] ucode_rom [ 0:`UCODE_SIZE-1 ];
--- a/system/fpga_config/OrangeCrab_r0.2.1/pin_constraint.pcf
+++ b/system/fpga_config/OrangeCrab_r0.2.1/pin_constraint.pcf
@ -0,0 +1,254 @@
+LOCATE COMP "clk48" SITE "A9";
+IOBUF PORT "clk48" IO_TYPE=LVCMOS33;
+FREQUENCY PORT "clk48" 48.0 MHz;
+
+LOCATE COMP "ddram_a[0]" SITE "C4";
+IOBUF PORT "ddram_a[0]" SLEWRATE=FAST;
+IOBUF PORT "ddram_a[0]" IO_TYPE=SSTL135_I;
+LOCATE COMP "ddram_a[1]" SITE "D2";
+IOBUF PORT "ddram_a[1]" SLEWRATE=FAST;
+IOBUF PORT "ddram_a[1]" IO_TYPE=SSTL135_I;
+LOCATE COMP "ddram_a[2]" SITE "D3";
+IOBUF PORT "ddram_a[2]" SLEWRATE=FAST;
+IOBUF PORT "ddram_a[2]" IO_TYPE=SSTL135_I;
+LOCATE COMP "ddram_a[3]" SITE "A3";
+IOBUF PORT "ddram_a[3]" SLEWRATE=FAST;
+IOBUF PORT "ddram_a[3]" IO_TYPE=SSTL135_I;
+LOCATE COMP "ddram_a[4]" SITE "A4";
+IOBUF PORT "ddram_a[4]" SLEWRATE=FAST;
+IOBUF PORT "ddram_a[4]" IO_TYPE=SSTL135_I;
+LOCATE COMP "ddram_a[5]" SITE "D4";
+IOBUF PORT "ddram_a[5]" SLEWRATE=FAST;
+IOBUF PORT "ddram_a[5]" IO_TYPE=SSTL135_I;
+LOCATE COMP "ddram_a[6]" SITE "C3";
+IOBUF PORT "ddram_a[6]" SLEWRATE=FAST;
+IOBUF PORT "ddram_a[6]" IO_TYPE=SSTL135_I;
+LOCATE COMP "ddram_a[7]" SITE "B2";
+IOBUF PORT "ddram_a[7]" SLEWRATE=FAST;
+IOBUF PORT "ddram_a[7]" IO_TYPE=SSTL135_I;
+LOCATE COMP "ddram_a[8]" SITE "B1";
+IOBUF PORT "ddram_a[8]" SLEWRATE=FAST;
+IOBUF PORT "ddram_a[8]" IO_TYPE=SSTL135_I;
+LOCATE COMP "ddram_a[9]" SITE "D1";
+IOBUF PORT "ddram_a[9]" SLEWRATE=FAST;
+IOBUF PORT "ddram_a[9]" IO_TYPE=SSTL135_I;
+LOCATE COMP "ddram_a[10]" SITE "A7";
+IOBUF PORT "ddram_a[10]" SLEWRATE=FAST;
+IOBUF PORT "ddram_a[10]" IO_TYPE=SSTL135_I;
+LOCATE COMP "ddram_a[11]" SITE "C2";
+IOBUF PORT "ddram_a[11]" SLEWRATE=FAST;
+IOBUF PORT "ddram_a[11]" IO_TYPE=SSTL135_I;
+LOCATE COMP "ddram_a[12]" SITE "B6";
+IOBUF PORT "ddram_a[12]" SLEWRATE=FAST;
+IOBUF PORT "ddram_a[12]" IO_TYPE=SSTL135_I;
+LOCATE COMP "ddram_a[13]" SITE "C1";
+IOBUF PORT "ddram_a[13]" SLEWRATE=FAST;
+IOBUF PORT "ddram_a[13]" IO_TYPE=SSTL135_I;
+LOCATE COMP "ddram_a[14]" SITE "A2";
+IOBUF PORT "ddram_a[14]" SLEWRATE=FAST;
+IOBUF PORT "ddram_a[14]" IO_TYPE=SSTL135_I;
+LOCATE COMP "ddram_a[15]" SITE "C7";
+IOBUF PORT "ddram_a[15]" SLEWRATE=FAST;
+IOBUF PORT "ddram_a[15]" IO_TYPE=SSTL135_I;
+LOCATE COMP "ddram_ba[0]" SITE "D6";
+IOBUF PORT "ddram_ba[0]" SLEWRATE=FAST;
+IOBUF PORT "ddram_ba[0]" IO_TYPE=SSTL135_I;
+LOCATE COMP "ddram_ba[1]" SITE "B7";
+IOBUF PORT "ddram_ba[1]" SLEWRATE=FAST;
+IOBUF PORT "ddram_ba[1]" IO_TYPE=SSTL135_I;
+LOCATE COMP "ddram_ba[2]" SITE "A6";
+IOBUF PORT "ddram_ba[2]" SLEWRATE=FAST;
+IOBUF PORT "ddram_ba[2]" IO_TYPE=SSTL135_I;
+LOCATE COMP "ddram_ras_n" SITE "C12";
+IOBUF PORT "ddram_ras_n" SLEWRATE=FAST;
+IOBUF PORT "ddram_ras_n" IO_TYPE=SSTL135_I;
+LOCATE COMP "ddram_cas_n" SITE "D13";
+IOBUF PORT "ddram_cas_n" SLEWRATE=FAST;
+IOBUF PORT "ddram_cas_n" IO_TYPE=SSTL135_I;
+LOCATE COMP "ddram_we_n" SITE "B12";
+IOBUF PORT "ddram_we_n" SLEWRATE=FAST;
+IOBUF PORT "ddram_we_n" IO_TYPE=SSTL135_I;
+LOCATE COMP "ddram_cs_n" SITE "A12";
+IOBUF PORT "ddram_cs_n" SLEWRATE=FAST;
+IOBUF PORT "ddram_cs_n" IO_TYPE=SSTL135_I;
+LOCATE COMP "ddram_dm[0]" SITE "D16";
+IOBUF PORT "ddram_dm[0]" SLEWRATE=FAST;
+IOBUF PORT "ddram_dm[0]" IO_TYPE=SSTL135_I;
+LOCATE COMP "ddram_dm[1]" SITE "G16";
+IOBUF PORT "ddram_dm[1]" SLEWRATE=FAST;
+IOBUF PORT "ddram_dm[1]" IO_TYPE=SSTL135_I;
+LOCATE COMP "ddram_dq[0]" SITE "C17";
+IOBUF PORT "ddram_dq[0]" SLEWRATE=FAST;
+IOBUF PORT "ddram_dq[0]" IO_TYPE=SSTL135_I;
+IOBUF PORT "ddram_dq[0]" TERMINATION=OFF;
+LOCATE COMP "ddram_dq[1]" SITE "D15";
+IOBUF PORT "ddram_dq[1]" SLEWRATE=FAST;
+IOBUF PORT "ddram_dq[1]" IO_TYPE=SSTL135_I;
+IOBUF PORT "ddram_dq[1]" TERMINATION=OFF;
+LOCATE COMP "ddram_dq[2]" SITE "B17";
+IOBUF PORT "ddram_dq[2]" SLEWRATE=FAST;
+IOBUF PORT "ddram_dq[2]" IO_TYPE=SSTL135_I;
+IOBUF PORT "ddram_dq[2]" TERMINATION=OFF;
+LOCATE COMP "ddram_dq[3]" SITE "C16";
+IOBUF PORT "ddram_dq[3]" SLEWRATE=FAST;
+IOBUF PORT "ddram_dq[3]" IO_TYPE=SSTL135_I;
+IOBUF PORT "ddram_dq[3]" TERMINATION=OFF;
+LOCATE COMP "ddram_dq[4]" SITE "A15";
+IOBUF PORT "ddram_dq[4]" SLEWRATE=FAST;
+IOBUF PORT "ddram_dq[4]" IO_TYPE=SSTL135_I;
+IOBUF PORT "ddram_dq[4]" TERMINATION=OFF;
+LOCATE COMP "ddram_dq[5]" SITE "B13";
+IOBUF PORT "ddram_dq[5]" SLEWRATE=FAST;
+IOBUF PORT "ddram_dq[5]" IO_TYPE=SSTL135_I;
+IOBUF PORT "ddram_dq[5]" TERMINATION=OFF;
+LOCATE COMP "ddram_dq[6]" SITE "A17";
+IOBUF PORT "ddram_dq[6]" SLEWRATE=FAST;
+IOBUF PORT "ddram_dq[6]" IO_TYPE=SSTL135_I;
+IOBUF PORT "ddram_dq[6]" TERMINATION=OFF;
+LOCATE COMP "ddram_dq[7]" SITE "A13";
+IOBUF PORT "ddram_dq[7]" SLEWRATE=FAST;
+IOBUF PORT "ddram_dq[7]" IO_TYPE=SSTL135_I;
+IOBUF PORT "ddram_dq[7]" TERMINATION=OFF;
+LOCATE COMP "ddram_dq[8]" SITE "F17";
+IOBUF PORT "ddram_dq[8]" SLEWRATE=FAST;
+IOBUF PORT "ddram_dq[8]" IO_TYPE=SSTL135_I;
+IOBUF PORT "ddram_dq[8]" TERMINATION=OFF;
+LOCATE COMP "ddram_dq[9]" SITE "F16";
+IOBUF PORT "ddram_dq[9]" SLEWRATE=FAST;
+IOBUF PORT "ddram_dq[9]" IO_TYPE=SSTL135_I;
+IOBUF PORT "ddram_dq[9]" TERMINATION=OFF;
+LOCATE COMP "ddram_dq[10]" SITE "G15";
+IOBUF PORT "ddram_dq[10]" SLEWRATE=FAST;
+IOBUF PORT "ddram_dq[10]" IO_TYPE=SSTL135_I;
+IOBUF PORT "ddram_dq[10]" TERMINATION=OFF;
+LOCATE COMP "ddram_dq[11]" SITE "F15";
+IOBUF PORT "ddram_dq[11]" SLEWRATE=FAST;
+IOBUF PORT "ddram_dq[11]" IO_TYPE=SSTL135_I;
+IOBUF PORT "ddram_dq[11]" TERMINATION=OFF;
+LOCATE COMP "ddram_dq[12]" SITE "J16";
+IOBUF PORT "ddram_dq[12]" SLEWRATE=FAST;
+IOBUF PORT "ddram_dq[12]" IO_TYPE=SSTL135_I;
+IOBUF PORT "ddram_dq[12]" TERMINATION=OFF;
+LOCATE COMP "ddram_dq[13]" SITE "C18";
+IOBUF PORT "ddram_dq[13]" SLEWRATE=FAST;
+IOBUF PORT "ddram_dq[13]" IO_TYPE=SSTL135_I;
+IOBUF PORT "ddram_dq[13]" TERMINATION=OFF;
+LOCATE COMP "ddram_dq[14]" SITE "H16";
+IOBUF PORT "ddram_dq[14]" SLEWRATE=FAST;
+IOBUF PORT "ddram_dq[14]" IO_TYPE=SSTL135_I;
+IOBUF PORT "ddram_dq[14]" TERMINATION=OFF;
+LOCATE COMP "ddram_dq[15]" SITE "F18";
+IOBUF PORT "ddram_dq[15]" SLEWRATE=FAST;
+IOBUF PORT "ddram_dq[15]" IO_TYPE=SSTL135_I;
+IOBUF PORT "ddram_dq[15]" TERMINATION=OFF;
+LOCATE COMP "ddram_dqs_p[0]" SITE "B15";
+IOBUF PORT "ddram_dqs_p[0]" SLEWRATE=FAST;
+IOBUF PORT "ddram_dqs_p[0]" IO_TYPE=SSTL135D_I;
+IOBUF PORT "ddram_dqs_p[0]" TERMINATION=OFF;
+IOBUF PORT "ddram_dqs_p[0]" DIFFRESISTOR=100;
+LOCATE COMP "ddram_dqs_p[1]" SITE "G18";
+IOBUF PORT "ddram_dqs_p[1]" SLEWRATE=FAST;
+IOBUF PORT "ddram_dqs_p[1]" IO_TYPE=SSTL135D_I;
+IOBUF PORT "ddram_dqs_p[1]" TERMINATION=OFF;
+IOBUF PORT "ddram_dqs_p[1]" DIFFRESISTOR=100;
+LOCATE COMP "ddram_clk_p" SITE "J18";
+IOBUF PORT "ddram_clk_p" SLEWRATE=FAST;
+IOBUF PORT "ddram_clk_p" IO_TYPE=SSTL135D_I;
+LOCATE COMP "ddram_cke" SITE "D18";
+IOBUF PORT "ddram_cke" SLEWRATE=FAST;
+IOBUF PORT "ddram_cke" IO_TYPE=SSTL135_I;
+LOCATE COMP "ddram_odt" SITE "C13";
+IOBUF PORT "ddram_odt" SLEWRATE=FAST;
+IOBUF PORT "ddram_odt" IO_TYPE=SSTL135_I;
+LOCATE COMP "ddram_reset_n" SITE "L18";
+IOBUF PORT "ddram_reset_n" SLEWRATE=FAST;
+IOBUF PORT "ddram_reset_n" IO_TYPE=SSTL135_I;
+LOCATE COMP "ddram_vccio[0]" SITE "K16";
+IOBUF PORT "ddram_vccio[0]" SLEWRATE=FAST;
+IOBUF PORT "ddram_vccio[0]" IO_TYPE=SSTL135_II;
+LOCATE COMP "ddram_vccio[1]" SITE "D17";
+IOBUF PORT "ddram_vccio[1]" SLEWRATE=FAST;
+IOBUF PORT "ddram_vccio[1]" IO_TYPE=SSTL135_II;
+LOCATE COMP "ddram_vccio[2]" SITE "K15";
+IOBUF PORT "ddram_vccio[2]" SLEWRATE=FAST;
+IOBUF PORT "ddram_vccio[2]" IO_TYPE=SSTL135_II;
+LOCATE COMP "ddram_vccio[3]" SITE "K17";
+IOBUF PORT "ddram_vccio[3]" SLEWRATE=FAST;
+IOBUF PORT "ddram_vccio[3]" IO_TYPE=SSTL135_II;
+LOCATE COMP "ddram_vccio[4]" SITE "B18";
+IOBUF PORT "ddram_vccio[4]" SLEWRATE=FAST;
+IOBUF PORT "ddram_vccio[4]" IO_TYPE=SSTL135_II;
+LOCATE COMP "ddram_vccio[5]" SITE "C6";
+IOBUF PORT "ddram_vccio[5]" SLEWRATE=FAST;
+IOBUF PORT "ddram_vccio[5]" IO_TYPE=SSTL135_II;
+LOCATE COMP "ddram_gnd[0]" SITE "L15";
+IOBUF PORT "ddram_gnd[0]" SLEWRATE=FAST;
+IOBUF PORT "ddram_gnd[0]" IO_TYPE=SSTL135_II;
+LOCATE COMP "ddram_gnd[1]" SITE "L16";
+IOBUF PORT "ddram_gnd[1]" SLEWRATE=FAST;
+IOBUF PORT "ddram_gnd[1]" IO_TYPE=SSTL135_II;
+LOCATE COMP "rgb_led0_r" SITE "K4";
+IOBUF PORT "rgb_led0_r" IO_TYPE=LVCMOS33;
+LOCATE COMP "rgb_led0_g" SITE "M3";
+IOBUF PORT "rgb_led0_g" IO_TYPE=LVCMOS33;
+LOCATE COMP "rgb_led0_b" SITE "J3";
+IOBUF PORT "rgb_led0_b" IO_TYPE=LVCMOS33;
+LOCATE COMP "gpio_0" SITE "N17";
+IOBUF PORT "gpio_0" IO_TYPE=LVCMOS33;
+IOBUF PORT "gpio_0" PULLMODE=DOWN;
+LOCATE COMP "gpio_1" SITE "M18";
+IOBUF PORT "gpio_1" IO_TYPE=LVCMOS33;
+IOBUF PORT "gpio_1" PULLMODE=DOWN;
+LOCATE COMP "gpio_5" SITE "B10";
+IOBUF PORT "gpio_5" IO_TYPE=LVCMOS33;
+IOBUF PORT "gpio_5" PULLMODE=DOWN;
+LOCATE COMP "gpio_6" SITE "B9";
+IOBUF PORT "gpio_6" IO_TYPE=LVCMOS33;
+IOBUF PORT "gpio_6" PULLMODE=DOWN;
+LOCATE COMP "gpio_9" SITE "C8";
+IOBUF PORT "gpio_9" IO_TYPE=LVCMOS33;
+IOBUF PORT "gpio_9" PULLMODE=DOWN;
+LOCATE COMP "gpio_10" SITE "B8";
+IOBUF PORT "gpio_10" IO_TYPE=LVCMOS33;
+IOBUF PORT "gpio_10" PULLMODE=DOWN;
+LOCATE COMP "gpio_11" SITE "A8";
+IOBUF PORT "gpio_11" IO_TYPE=LVCMOS33;
+IOBUF PORT "gpio_11" PULLMODE=DOWN;
+LOCATE COMP "gpio_12" SITE "H2";
+IOBUF PORT "gpio_12" IO_TYPE=LVCMOS33;
+IOBUF PORT "gpio_12" PULLMODE=DOWN;
+LOCATE COMP "gpio_13" SITE "J2";
+IOBUF PORT "gpio_13" IO_TYPE=LVCMOS33;
+IOBUF PORT "gpio_13" PULLMODE=DOWN;
+LOCATE COMP "gpio_a0" SITE "L4";
+IOBUF PORT "gpio_a0" IO_TYPE=LVCMOS33;
+IOBUF PORT "gpio_a0" PULLMODE=DOWN;
+LOCATE COMP "gpio_a1" SITE "N3";
+IOBUF PORT "gpio_a1" IO_TYPE=LVCMOS33;
+IOBUF PORT "gpio_a1" PULLMODE=DOWN;
+LOCATE COMP "gpio_a2" SITE "N4";
+IOBUF PORT "gpio_a2" IO_TYPE=LVCMOS33;
+IOBUF PORT "gpio_a2" PULLMODE=DOWN;
+LOCATE COMP "gpio_a3" SITE "H4";
+IOBUF PORT "gpio_a3" IO_TYPE=LVCMOS33;
+IOBUF PORT "gpio_a3" PULLMODE=DOWN;
+LOCATE COMP "usr_btn" SITE "J17";
+IOBUF PORT "usr_btn" IO_TYPE=SSTL135_I;
+LOCATE COMP "rst_n" SITE "V17";
+IOBUF PORT "rst_n" IO_TYPE=LVCMOS33;
+LOCATE COMP "spiflash4x_cs_n" SITE "U17";
+IOBUF PORT "spiflash4x_cs_n" IO_TYPE=LVCMOS33;
+LOCATE COMP "spiflash4x_dq[0]" SITE "U18";
+IOBUF PORT "spiflash4x_dq[0]" IO_TYPE=LVCMOS33;
+LOCATE COMP "spiflash4x_dq[1]" SITE "T18";
+IOBUF PORT "spiflash4x_dq[1]" IO_TYPE=LVCMOS33;
+LOCATE COMP "spiflash4x_dq[2]" SITE "R18";
+IOBUF PORT "spiflash4x_dq[2]" IO_TYPE=LVCMOS33;
+LOCATE COMP "spiflash4x_dq[3]" SITE "N18";
+IOBUF PORT "spiflash4x_dq[3]" IO_TYPE=LVCMOS33;
+LOCATE COMP "usb_d_p" SITE "N1";
+IOBUF PORT "usb_d_p" IO_TYPE=LVCMOS33;
+LOCATE COMP "usb_d_n" SITE "M2";
+IOBUF PORT "usb_d_n" IO_TYPE=LVCMOS33;
+LOCATE COMP "usb_pullup" SITE "N2";
+IOBUF PORT "usb_pullup" IO_TYPE=LVCMOS33;
--- a/system/memory.v
+++ b/system/memory.v
@ -25,12 +25,17 @@ module doublemem(input [19:0] address,inout wire [15:0] data ,input rd,input wr,
 reg [15:0] memory [0:32768];

 initial begin
+`ifndef YOSYS
 	string boot_code;
 	if(!$value$plusargs("BOOT_CODE=%s",boot_code))begin
 		$display("No boot code specified. Please add +BOOT_CODE=<path> to your vvp args");
 		$finish;
 	end
 	$readmemh(boot_code, memory,0,32767);
+`else
+	//TODO: don't have it hard coded
+	$readmemh("boot_code.txt", memory,0,32767);
+`endif
 end

 assign data[7:0] = !address[0:0] & !rd & !cs ? memory[address[16:1]][15:8]  : 8'hz;
--- a/system/processor.v
+++ b/system/processor.v
@ -20,6 +20,7 @@
 `include "exec_state_def.v"
 `include "alu_header.v"
 `include "config.v"
+`include "error_header.v"

 //HALT: active high
 //IOMEM: 1=IO  0=MEM
--- a/system/system.v
+++ b/system/system.v
@ -50,21 +50,27 @@ doublemem sysmem(address_bus,data_bus,rd,wr,BHE,IOMEM);
 string stats_name,version,commit;
 integer json_file_descriptor;
 `endif
+
+`ifndef YOSYS
 string waveform_name;
+`endif
+
 initial begin
-	if($value$plusargs("WAVEFORM=%s",waveform_name))begin
-		$dumpfile(waveform_name);
-		$dumpvars(0,p,cycles);
-	end
-	`ifdef OTUPUT_JSON_STATISTICS
-	if(!$value$plusargs("VERSION=%s",version)) version="unkown";
-	if(!$value$plusargs("COMMIT=%s",commit)) commit="unkown";
-	if($value$plusargs("STATS=%s",stats_name))begin
-		json_file_descriptor=$fopen(stats_name,"w");
-		$fdisplay(json_file_descriptor,"{\n\"L1_size\":%0d,\n\"9086 verison\":\"%s\",\n\"latest commit\":\"%s\",\n\"Cycles\":[",$rtoi($pow(2,`L1_CACHE_SIZE)),version,commit);
-		first_json_cycle = 1;
-	end else
-		json_file_descriptor=0;
+	`ifndef YOSYS
+		if($value$plusargs("WAVEFORM=%s",waveform_name))begin
+			$dumpfile(waveform_name);
+			$dumpvars(0,p,cycles);
+		end
+		`ifdef OTUPUT_JSON_STATISTICS
+		if(!$value$plusargs("VERSION=%s",version)) version="unkown";
+		if(!$value$plusargs("COMMIT=%s",commit)) commit="unkown";
+		if($value$plusargs("STATS=%s",stats_name))begin
+			json_file_descriptor=$fopen(stats_name,"w");
+			$fdisplay(json_file_descriptor,"{\n\"L1_size\":%0d,\n\"9086 verison\":\"%s\",\n\"latest commit\":\"%s\",\n\"Cycles\":[",$rtoi($pow(2,`L1_CACHE_SIZE)),version,commit);
+			first_json_cycle = 1;
+		end else
+			json_file_descriptor=0;
+		`endif
 	`endif
 	sane=0;
 	finish=0;
@ -105,11 +111,16 @@ end
 `endif

 reg [1:0] finish;
+
+`ifndef YOSYS
 string memdump_name;
+`endif
 always @(posedge HALT) begin
-	if($value$plusargs("MEMDUMP=%s",memdump_name))begin
-		$writememh(memdump_name, sysmem.memory,0,32767);
-	end
+	`ifndef YOSYS
+		if($value$plusargs("MEMDUMP=%s",memdump_name))begin
+			$writememh(memdump_name, sysmem.memory,0,32767);
+		end
+	`endif
 	finish<=2'd1;
 end

@ -140,7 +151,11 @@ always @(posedge clock) begin
 					$fdisplay(json_file_descriptor,"],\n\"Total Cycles\":%0d,\n\"Instructions run\":%0d\n}",cycles-1,instruction_count_temp);
 			`endif
 		end
-		2'd3: $finish;
+		2'd3: begin
+		`ifndef SYNTHESIS
+			$finish;
+		`endif
+		end
 	endcase
 end

@ -162,9 +177,11 @@ always @( ERROR ) begin
 			end
 		endcase
 		$display("Cycles run for: %0d",cycles-1);
-		if($value$plusargs("MEMDUMP=%s",memdump_name))begin
-			$writememh(memdump_name, system.sysmem.memory,0,32767);
-		end
+		`ifndef SYNTHESIS
+			if($value$plusargs("MEMDUMP=%s",memdump_name))begin
+				$writememh(memdump_name, system.sysmem.memory,0,32767);
+			end
+		`endif
 		finish<=2'd1;
 	end
 end