Added support to the build system for synthesising, place and routing, serialising and uploading the design to a Lattice ECP5 OrangeCrab FPGA
This commit is contained in:
parent
85512d5ace
commit
5feee9de57
4
.gitignore
vendored
4
.gitignore
vendored
@ -6,6 +6,10 @@
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*.swp
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*.swp
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*.memdump
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*.memdump
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*.json
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*.json
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*.dfu
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*.bit
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abc.history
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system/synth_ecp5_out.config
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boot_code/*.bin
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boot_code/*.bin
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boot_code/*.txt
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boot_code/*.txt
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system/boot_code.bin
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system/boot_code.bin
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3
Makefile
3
Makefile
@ -47,3 +47,6 @@ ${VERILATOR_BIN}:
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clean:
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clean:
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${Q}make ${MAKEOPTS} -C system clean
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${Q}make ${MAKEOPTS} -C system clean
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${Q}make ${MAKEOPTS} -C boot_code clean
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${Q}make ${MAKEOPTS} -C boot_code clean
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upload:
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make -C system upload
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@ -32,7 +32,13 @@ After that you can run `make` on the top level directory and it should build eve
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<img width="700" style=" margin: 10px 0px 10px 10px;" alt="9086 logo" src="readme_files/9086_overview.svg">
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<img width="700" style=" margin: 10px 0px 10px 10px;" alt="9086 logo" src="readme_files/9086_overview.svg">
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### License
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### License
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All parts of this project are licensed under the GNU General Public License version 3 or later
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All parts of this project and files in this repository are licensed under the GNU General Public License version 3 or later
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Efthymios Kritikos is the copyright owner for all files except the following:
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| File | Copyright owner | Original license |
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| :-----------------------------------------------------: | :-------------: | :--------------: |
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| system/fpga_config/OrangeCrab_r0.2.1/pin_constraint.pcf | Greg Davill | MIT |
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### Version names
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### Version names
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The version name consist of three numbers:
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The version name consist of three numbers:
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28
common.mk
28
common.mk
@ -1,24 +1,50 @@
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.PRECIOUS:${BOOT_CODE}
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.PRECIOUS:${BOOT_CODE}
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########## BUILD OPTIONS ##########
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QUIET=1
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QUIET=1
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# QUIET: 1=clean, non-verbose output
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# QUIET: 1=clean, non-verbose output
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# 2=normal make output
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# 2=normal make output
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####### SIMULATION OPTIONS ########
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SIM=VERILATOR
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SIM=VERILATOR
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# SIM: VERILATOR: use Verilator
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# SIM: VERILATOR: use Verilator
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# ICARUS: use Icarus Verilog
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# ICARUS: use Icarus Verilog
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NUMACTL=#numactl -m 0 -C 0,1 --
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NUMACTL=#numactl -m 0 -C 0,1 --
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######## SYNTHESIS OPTIONS ########
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FPGA_BOARD=OrangeCrab_r0.2.1
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# BOARD: the options are the directories in system/fpga_config/.
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# Select the one you have
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#### ECP5 specific ####
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ECP5_DEVICE=25F
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# ECP5_DEVICE: 25F: Create bitstream for the LFE5U-25F
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# 85F: Create bitstream for the LFE5U-85F
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ECP5_PACKAGE=CSFBGA285
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# ECP5_PACKAGE: CSFBGA285: The one used in OrangeCrab
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VERSION="v0.2.0"
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VERSION="v0.2.0"
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COMMIT=$(shell git log --pretty=format:'%H' -1 |cat)
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COMMIT=$(shell git log --pretty=format:'%H' -1 |cat)
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ifeq "${QUIET}" "1"
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ifeq "${QUIET}" "1"
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QUIET_AS = @echo ' AS '$@;
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QUIET_AS = @echo ' AS '$@;
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QUIET_CC = @echo ' CC '$@;
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QUIET_VVP = @echo ' VVP '$@;
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QUIET_VVP = @echo ' VVP '$@;
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QUIET_IVERILOG = @echo ' IVERILOG '$@;
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QUIET_IVERILOG = @echo ' IVERILOG '$@;
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QUIET_VERILATOR = @echo ' VERILATOR '$@;
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QUIET_VERILATOR = @echo ' VERILATOR '$@;
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QUIET_CC = @echo ' CC '$@;
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QUIET_YOSYS = @echo ' YOSYS '$@;
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QUIET_NEXTPNR = @echo ' NEXTPNR '$@;
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QUIET_ECPPACK = @echo ' ECPPACK '$@;
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QUIET_DFU_SUFFIX = @echo ' DFU-SUFFIX '$@;
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QUIET_DFU_UTIL = @echo ' DFU-UTIL '$<;
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QUIET_CLEAN = @printf ' CLEAN %s\n' $1;
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QUIET_CLEAN = @printf ' CLEAN %s\n' $1;
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QUIET_VERILATOR_RUN = @printf ' %s %s\n' $1 $2;
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QUIET_VERILATOR_RUN = @printf ' %s %s\n' $1 $2;
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Q = @
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Q = @
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@ -55,7 +55,44 @@ ${VERILATOR_BIN}.mk: ${VERILATOR_TESTBENCH} ${TOP_LEVEL_SOURCE} ${SOURCES} ${INC
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${QUIET_VERILATOR}
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${QUIET_VERILATOR}
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${Q}verilator -DCALCULATE_IPC -DOTUPUT_JSON_STATISTICS ${VERILATOR_OPTS} $^
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${Q}verilator -DCALCULATE_IPC -DOTUPUT_JSON_STATISTICS ${VERILATOR_OPTS} $^
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# Synthesis and bitstream creation for ECP5
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ifeq "${ECP5_DEVICE}" "25F"
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NEXTPNR_ECP5_DEV=--25k
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else ifeq "${ECP5_DEVICE}" "85F"
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NEXTPNR_ECP5_DEV=--85k
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else
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$(error invalid ECP5 device ${ECP5_DEVICE})
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endif
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ECP5_TARGETS=synth_ecp5.json synth_ecp5_out.config synth_ecp5.bit synth_ecp5.dfu
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ECP5_TARGETS+=abc.history # created from yosys
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synth_ecp5.json: ${SOURCES} ${TOP_LEVEL_SOURCE} ${INCLUDES} boot_code.txt
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${QUIET_YOSYS}
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${Q} yosys -q -p 'read -sv '"${SOURCES} ${TOP_LEVEL_SOURCE} ; synth_ecp5 -json $@"
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synth_ecp5_out.config:synth_ecp5.json
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${QUIET_NEXTPNR}
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${Q} nextpnr-ecp5 --Werror -q --json $< --textcfg $@ ${NEXTPNR_ECP5_DEV} --package ${ECP5_PACKAGE} --lpf fpga_config/${FPGA_BOARD}/pin_constraint.pcf
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synth_ecp5.bit:synth_ecp5_out.config
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${QUIET_ECPPACK}
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${Q}ecppack --compress --freq 38.8 --input $< --bit $@
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synth_ecp5.dfu:synth_ecp5.bit
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${QUIET_DFU_SUFFIX}
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${Q}cp "$<" synth_ecp5.temp_dfu
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@#From some testing, dfu-suffix does output errors to stderr so this should be fine
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${Q}dfu-suffix --vid 1209 --pid 5af0 --add synth_ecp5.temp_dfu > /dev/null
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${Q}mv synth_ecp5.temp_dfu "$@"
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upload_orangecrab:synth_ecp5.dfu
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${QUIET_DFU_UTIL}
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${Q}stdbuf -o0 dfu-util --download "$<" |stdbuf -o0 tr '\n' '\a' | stdbuf -o0 tr '\r' '\n' | grep Download --line-buffered | stdbuf -o0 tr '\n' '\r' |stdbuf -o0 tr '\a' '\n'
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upload: upload_orangecrab
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.PHONY: clean
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.PHONY: clean
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clean:
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clean:
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$(call QUIET_CLEAN,system)
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$(call QUIET_CLEAN,system)
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${Q}rm -rf ${SYSTEM_VVP} *.fst boot_code.txt boot_code.bin *memdump *memdumptxt obj_dir *json
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${Q}rm -rf ${SYSTEM_VVP} *.fst boot_code.txt boot_code.bin *memdump *memdumptxt obj_dir *json ${ECP5_TARGETS}
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@ -224,6 +224,7 @@ module microcode(
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);
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);
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initial begin
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initial begin
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`ifndef YOSYS
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string ucode_path;
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string ucode_path;
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if($value$plusargs("MICROCODE=%s",ucode_path))begin
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if($value$plusargs("MICROCODE=%s",ucode_path))begin
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$readmemb(ucode_path,ucode_rom,0,`UCODE_SIZE-1);
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$readmemb(ucode_path,ucode_rom,0,`UCODE_SIZE-1);
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@ -231,6 +232,10 @@ initial begin
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$display("Please supply microcode rom file as a runtime vvp argument +MICROCODE=<path>");
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$display("Please supply microcode rom file as a runtime vvp argument +MICROCODE=<path>");
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$finish;
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$finish;
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end
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end
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`else
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//TODO: don't have it hard coded
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$readmemb("ucode.txt",ucode_rom,0,`UCODE_SIZE-1);
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`endif
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end
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end
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reg [`UCODE_DATA_BITS-1:0] ucode_rom [ 0:`UCODE_SIZE-1 ];
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reg [`UCODE_DATA_BITS-1:0] ucode_rom [ 0:`UCODE_SIZE-1 ];
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254
system/fpga_config/OrangeCrab_r0.2.1/pin_constraint.pcf
Normal file
254
system/fpga_config/OrangeCrab_r0.2.1/pin_constraint.pcf
Normal file
@ -0,0 +1,254 @@
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LOCATE COMP "clk48" SITE "A9";
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IOBUF PORT "clk48" IO_TYPE=LVCMOS33;
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FREQUENCY PORT "clk48" 48.0 MHz;
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LOCATE COMP "ddram_a[0]" SITE "C4";
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IOBUF PORT "ddram_a[0]" SLEWRATE=FAST;
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IOBUF PORT "ddram_a[0]" IO_TYPE=SSTL135_I;
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LOCATE COMP "ddram_a[1]" SITE "D2";
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IOBUF PORT "ddram_a[1]" SLEWRATE=FAST;
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IOBUF PORT "ddram_a[1]" IO_TYPE=SSTL135_I;
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LOCATE COMP "ddram_a[2]" SITE "D3";
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IOBUF PORT "ddram_a[2]" SLEWRATE=FAST;
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IOBUF PORT "ddram_a[2]" IO_TYPE=SSTL135_I;
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LOCATE COMP "ddram_a[3]" SITE "A3";
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IOBUF PORT "ddram_a[3]" SLEWRATE=FAST;
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IOBUF PORT "ddram_a[3]" IO_TYPE=SSTL135_I;
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LOCATE COMP "ddram_a[4]" SITE "A4";
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IOBUF PORT "ddram_a[4]" SLEWRATE=FAST;
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IOBUF PORT "ddram_a[4]" IO_TYPE=SSTL135_I;
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LOCATE COMP "ddram_a[5]" SITE "D4";
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IOBUF PORT "ddram_a[5]" SLEWRATE=FAST;
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IOBUF PORT "ddram_a[5]" IO_TYPE=SSTL135_I;
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LOCATE COMP "ddram_a[6]" SITE "C3";
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IOBUF PORT "ddram_a[6]" SLEWRATE=FAST;
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IOBUF PORT "ddram_a[6]" IO_TYPE=SSTL135_I;
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LOCATE COMP "ddram_a[7]" SITE "B2";
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IOBUF PORT "ddram_a[7]" SLEWRATE=FAST;
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IOBUF PORT "ddram_a[7]" IO_TYPE=SSTL135_I;
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LOCATE COMP "ddram_a[8]" SITE "B1";
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IOBUF PORT "ddram_a[8]" SLEWRATE=FAST;
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IOBUF PORT "ddram_a[8]" IO_TYPE=SSTL135_I;
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LOCATE COMP "ddram_a[9]" SITE "D1";
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IOBUF PORT "ddram_a[9]" SLEWRATE=FAST;
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IOBUF PORT "ddram_a[9]" IO_TYPE=SSTL135_I;
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LOCATE COMP "ddram_a[10]" SITE "A7";
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IOBUF PORT "ddram_a[10]" SLEWRATE=FAST;
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IOBUF PORT "ddram_a[10]" IO_TYPE=SSTL135_I;
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LOCATE COMP "ddram_a[11]" SITE "C2";
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IOBUF PORT "ddram_a[11]" SLEWRATE=FAST;
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IOBUF PORT "ddram_a[11]" IO_TYPE=SSTL135_I;
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LOCATE COMP "ddram_a[12]" SITE "B6";
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IOBUF PORT "ddram_a[12]" SLEWRATE=FAST;
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IOBUF PORT "ddram_a[12]" IO_TYPE=SSTL135_I;
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LOCATE COMP "ddram_a[13]" SITE "C1";
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IOBUF PORT "ddram_a[13]" SLEWRATE=FAST;
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IOBUF PORT "ddram_a[13]" IO_TYPE=SSTL135_I;
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LOCATE COMP "ddram_a[14]" SITE "A2";
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IOBUF PORT "ddram_a[14]" SLEWRATE=FAST;
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IOBUF PORT "ddram_a[14]" IO_TYPE=SSTL135_I;
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LOCATE COMP "ddram_a[15]" SITE "C7";
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IOBUF PORT "ddram_a[15]" SLEWRATE=FAST;
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IOBUF PORT "ddram_a[15]" IO_TYPE=SSTL135_I;
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LOCATE COMP "ddram_ba[0]" SITE "D6";
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IOBUF PORT "ddram_ba[0]" SLEWRATE=FAST;
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IOBUF PORT "ddram_ba[0]" IO_TYPE=SSTL135_I;
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LOCATE COMP "ddram_ba[1]" SITE "B7";
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IOBUF PORT "ddram_ba[1]" SLEWRATE=FAST;
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IOBUF PORT "ddram_ba[1]" IO_TYPE=SSTL135_I;
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LOCATE COMP "ddram_ba[2]" SITE "A6";
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IOBUF PORT "ddram_ba[2]" SLEWRATE=FAST;
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IOBUF PORT "ddram_ba[2]" IO_TYPE=SSTL135_I;
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LOCATE COMP "ddram_ras_n" SITE "C12";
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IOBUF PORT "ddram_ras_n" SLEWRATE=FAST;
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IOBUF PORT "ddram_ras_n" IO_TYPE=SSTL135_I;
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LOCATE COMP "ddram_cas_n" SITE "D13";
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IOBUF PORT "ddram_cas_n" SLEWRATE=FAST;
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IOBUF PORT "ddram_cas_n" IO_TYPE=SSTL135_I;
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LOCATE COMP "ddram_we_n" SITE "B12";
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IOBUF PORT "ddram_we_n" SLEWRATE=FAST;
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IOBUF PORT "ddram_we_n" IO_TYPE=SSTL135_I;
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LOCATE COMP "ddram_cs_n" SITE "A12";
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IOBUF PORT "ddram_cs_n" SLEWRATE=FAST;
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IOBUF PORT "ddram_cs_n" IO_TYPE=SSTL135_I;
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LOCATE COMP "ddram_dm[0]" SITE "D16";
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IOBUF PORT "ddram_dm[0]" SLEWRATE=FAST;
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IOBUF PORT "ddram_dm[0]" IO_TYPE=SSTL135_I;
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LOCATE COMP "ddram_dm[1]" SITE "G16";
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IOBUF PORT "ddram_dm[1]" SLEWRATE=FAST;
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IOBUF PORT "ddram_dm[1]" IO_TYPE=SSTL135_I;
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LOCATE COMP "ddram_dq[0]" SITE "C17";
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IOBUF PORT "ddram_dq[0]" SLEWRATE=FAST;
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IOBUF PORT "ddram_dq[0]" IO_TYPE=SSTL135_I;
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IOBUF PORT "ddram_dq[0]" TERMINATION=OFF;
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LOCATE COMP "ddram_dq[1]" SITE "D15";
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IOBUF PORT "ddram_dq[1]" SLEWRATE=FAST;
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IOBUF PORT "ddram_dq[1]" IO_TYPE=SSTL135_I;
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IOBUF PORT "ddram_dq[1]" TERMINATION=OFF;
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LOCATE COMP "ddram_dq[2]" SITE "B17";
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IOBUF PORT "ddram_dq[2]" SLEWRATE=FAST;
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IOBUF PORT "ddram_dq[2]" IO_TYPE=SSTL135_I;
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IOBUF PORT "ddram_dq[2]" TERMINATION=OFF;
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LOCATE COMP "ddram_dq[3]" SITE "C16";
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IOBUF PORT "ddram_dq[3]" SLEWRATE=FAST;
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IOBUF PORT "ddram_dq[3]" IO_TYPE=SSTL135_I;
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IOBUF PORT "ddram_dq[3]" TERMINATION=OFF;
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LOCATE COMP "ddram_dq[4]" SITE "A15";
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IOBUF PORT "ddram_dq[4]" SLEWRATE=FAST;
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IOBUF PORT "ddram_dq[4]" IO_TYPE=SSTL135_I;
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IOBUF PORT "ddram_dq[4]" TERMINATION=OFF;
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LOCATE COMP "ddram_dq[5]" SITE "B13";
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IOBUF PORT "ddram_dq[5]" SLEWRATE=FAST;
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IOBUF PORT "ddram_dq[5]" IO_TYPE=SSTL135_I;
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IOBUF PORT "ddram_dq[5]" TERMINATION=OFF;
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LOCATE COMP "ddram_dq[6]" SITE "A17";
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IOBUF PORT "ddram_dq[6]" SLEWRATE=FAST;
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IOBUF PORT "ddram_dq[6]" IO_TYPE=SSTL135_I;
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IOBUF PORT "ddram_dq[6]" TERMINATION=OFF;
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LOCATE COMP "ddram_dq[7]" SITE "A13";
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IOBUF PORT "ddram_dq[7]" SLEWRATE=FAST;
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IOBUF PORT "ddram_dq[7]" IO_TYPE=SSTL135_I;
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IOBUF PORT "ddram_dq[7]" TERMINATION=OFF;
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LOCATE COMP "ddram_dq[8]" SITE "F17";
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IOBUF PORT "ddram_dq[8]" SLEWRATE=FAST;
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IOBUF PORT "ddram_dq[8]" IO_TYPE=SSTL135_I;
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IOBUF PORT "ddram_dq[8]" TERMINATION=OFF;
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LOCATE COMP "ddram_dq[9]" SITE "F16";
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IOBUF PORT "ddram_dq[9]" SLEWRATE=FAST;
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||||||
|
IOBUF PORT "ddram_dq[9]" IO_TYPE=SSTL135_I;
|
||||||
|
IOBUF PORT "ddram_dq[9]" TERMINATION=OFF;
|
||||||
|
LOCATE COMP "ddram_dq[10]" SITE "G15";
|
||||||
|
IOBUF PORT "ddram_dq[10]" SLEWRATE=FAST;
|
||||||
|
IOBUF PORT "ddram_dq[10]" IO_TYPE=SSTL135_I;
|
||||||
|
IOBUF PORT "ddram_dq[10]" TERMINATION=OFF;
|
||||||
|
LOCATE COMP "ddram_dq[11]" SITE "F15";
|
||||||
|
IOBUF PORT "ddram_dq[11]" SLEWRATE=FAST;
|
||||||
|
IOBUF PORT "ddram_dq[11]" IO_TYPE=SSTL135_I;
|
||||||
|
IOBUF PORT "ddram_dq[11]" TERMINATION=OFF;
|
||||||
|
LOCATE COMP "ddram_dq[12]" SITE "J16";
|
||||||
|
IOBUF PORT "ddram_dq[12]" SLEWRATE=FAST;
|
||||||
|
IOBUF PORT "ddram_dq[12]" IO_TYPE=SSTL135_I;
|
||||||
|
IOBUF PORT "ddram_dq[12]" TERMINATION=OFF;
|
||||||
|
LOCATE COMP "ddram_dq[13]" SITE "C18";
|
||||||
|
IOBUF PORT "ddram_dq[13]" SLEWRATE=FAST;
|
||||||
|
IOBUF PORT "ddram_dq[13]" IO_TYPE=SSTL135_I;
|
||||||
|
IOBUF PORT "ddram_dq[13]" TERMINATION=OFF;
|
||||||
|
LOCATE COMP "ddram_dq[14]" SITE "H16";
|
||||||
|
IOBUF PORT "ddram_dq[14]" SLEWRATE=FAST;
|
||||||
|
IOBUF PORT "ddram_dq[14]" IO_TYPE=SSTL135_I;
|
||||||
|
IOBUF PORT "ddram_dq[14]" TERMINATION=OFF;
|
||||||
|
LOCATE COMP "ddram_dq[15]" SITE "F18";
|
||||||
|
IOBUF PORT "ddram_dq[15]" SLEWRATE=FAST;
|
||||||
|
IOBUF PORT "ddram_dq[15]" IO_TYPE=SSTL135_I;
|
||||||
|
IOBUF PORT "ddram_dq[15]" TERMINATION=OFF;
|
||||||
|
LOCATE COMP "ddram_dqs_p[0]" SITE "B15";
|
||||||
|
IOBUF PORT "ddram_dqs_p[0]" SLEWRATE=FAST;
|
||||||
|
IOBUF PORT "ddram_dqs_p[0]" IO_TYPE=SSTL135D_I;
|
||||||
|
IOBUF PORT "ddram_dqs_p[0]" TERMINATION=OFF;
|
||||||
|
IOBUF PORT "ddram_dqs_p[0]" DIFFRESISTOR=100;
|
||||||
|
LOCATE COMP "ddram_dqs_p[1]" SITE "G18";
|
||||||
|
IOBUF PORT "ddram_dqs_p[1]" SLEWRATE=FAST;
|
||||||
|
IOBUF PORT "ddram_dqs_p[1]" IO_TYPE=SSTL135D_I;
|
||||||
|
IOBUF PORT "ddram_dqs_p[1]" TERMINATION=OFF;
|
||||||
|
IOBUF PORT "ddram_dqs_p[1]" DIFFRESISTOR=100;
|
||||||
|
LOCATE COMP "ddram_clk_p" SITE "J18";
|
||||||
|
IOBUF PORT "ddram_clk_p" SLEWRATE=FAST;
|
||||||
|
IOBUF PORT "ddram_clk_p" IO_TYPE=SSTL135D_I;
|
||||||
|
LOCATE COMP "ddram_cke" SITE "D18";
|
||||||
|
IOBUF PORT "ddram_cke" SLEWRATE=FAST;
|
||||||
|
IOBUF PORT "ddram_cke" IO_TYPE=SSTL135_I;
|
||||||
|
LOCATE COMP "ddram_odt" SITE "C13";
|
||||||
|
IOBUF PORT "ddram_odt" SLEWRATE=FAST;
|
||||||
|
IOBUF PORT "ddram_odt" IO_TYPE=SSTL135_I;
|
||||||
|
LOCATE COMP "ddram_reset_n" SITE "L18";
|
||||||
|
IOBUF PORT "ddram_reset_n" SLEWRATE=FAST;
|
||||||
|
IOBUF PORT "ddram_reset_n" IO_TYPE=SSTL135_I;
|
||||||
|
LOCATE COMP "ddram_vccio[0]" SITE "K16";
|
||||||
|
IOBUF PORT "ddram_vccio[0]" SLEWRATE=FAST;
|
||||||
|
IOBUF PORT "ddram_vccio[0]" IO_TYPE=SSTL135_II;
|
||||||
|
LOCATE COMP "ddram_vccio[1]" SITE "D17";
|
||||||
|
IOBUF PORT "ddram_vccio[1]" SLEWRATE=FAST;
|
||||||
|
IOBUF PORT "ddram_vccio[1]" IO_TYPE=SSTL135_II;
|
||||||
|
LOCATE COMP "ddram_vccio[2]" SITE "K15";
|
||||||
|
IOBUF PORT "ddram_vccio[2]" SLEWRATE=FAST;
|
||||||
|
IOBUF PORT "ddram_vccio[2]" IO_TYPE=SSTL135_II;
|
||||||
|
LOCATE COMP "ddram_vccio[3]" SITE "K17";
|
||||||
|
IOBUF PORT "ddram_vccio[3]" SLEWRATE=FAST;
|
||||||
|
IOBUF PORT "ddram_vccio[3]" IO_TYPE=SSTL135_II;
|
||||||
|
LOCATE COMP "ddram_vccio[4]" SITE "B18";
|
||||||
|
IOBUF PORT "ddram_vccio[4]" SLEWRATE=FAST;
|
||||||
|
IOBUF PORT "ddram_vccio[4]" IO_TYPE=SSTL135_II;
|
||||||
|
LOCATE COMP "ddram_vccio[5]" SITE "C6";
|
||||||
|
IOBUF PORT "ddram_vccio[5]" SLEWRATE=FAST;
|
||||||
|
IOBUF PORT "ddram_vccio[5]" IO_TYPE=SSTL135_II;
|
||||||
|
LOCATE COMP "ddram_gnd[0]" SITE "L15";
|
||||||
|
IOBUF PORT "ddram_gnd[0]" SLEWRATE=FAST;
|
||||||
|
IOBUF PORT "ddram_gnd[0]" IO_TYPE=SSTL135_II;
|
||||||
|
LOCATE COMP "ddram_gnd[1]" SITE "L16";
|
||||||
|
IOBUF PORT "ddram_gnd[1]" SLEWRATE=FAST;
|
||||||
|
IOBUF PORT "ddram_gnd[1]" IO_TYPE=SSTL135_II;
|
||||||
|
LOCATE COMP "rgb_led0_r" SITE "K4";
|
||||||
|
IOBUF PORT "rgb_led0_r" IO_TYPE=LVCMOS33;
|
||||||
|
LOCATE COMP "rgb_led0_g" SITE "M3";
|
||||||
|
IOBUF PORT "rgb_led0_g" IO_TYPE=LVCMOS33;
|
||||||
|
LOCATE COMP "rgb_led0_b" SITE "J3";
|
||||||
|
IOBUF PORT "rgb_led0_b" IO_TYPE=LVCMOS33;
|
||||||
|
LOCATE COMP "gpio_0" SITE "N17";
|
||||||
|
IOBUF PORT "gpio_0" IO_TYPE=LVCMOS33;
|
||||||
|
IOBUF PORT "gpio_0" PULLMODE=DOWN;
|
||||||
|
LOCATE COMP "gpio_1" SITE "M18";
|
||||||
|
IOBUF PORT "gpio_1" IO_TYPE=LVCMOS33;
|
||||||
|
IOBUF PORT "gpio_1" PULLMODE=DOWN;
|
||||||
|
LOCATE COMP "gpio_5" SITE "B10";
|
||||||
|
IOBUF PORT "gpio_5" IO_TYPE=LVCMOS33;
|
||||||
|
IOBUF PORT "gpio_5" PULLMODE=DOWN;
|
||||||
|
LOCATE COMP "gpio_6" SITE "B9";
|
||||||
|
IOBUF PORT "gpio_6" IO_TYPE=LVCMOS33;
|
||||||
|
IOBUF PORT "gpio_6" PULLMODE=DOWN;
|
||||||
|
LOCATE COMP "gpio_9" SITE "C8";
|
||||||
|
IOBUF PORT "gpio_9" IO_TYPE=LVCMOS33;
|
||||||
|
IOBUF PORT "gpio_9" PULLMODE=DOWN;
|
||||||
|
LOCATE COMP "gpio_10" SITE "B8";
|
||||||
|
IOBUF PORT "gpio_10" IO_TYPE=LVCMOS33;
|
||||||
|
IOBUF PORT "gpio_10" PULLMODE=DOWN;
|
||||||
|
LOCATE COMP "gpio_11" SITE "A8";
|
||||||
|
IOBUF PORT "gpio_11" IO_TYPE=LVCMOS33;
|
||||||
|
IOBUF PORT "gpio_11" PULLMODE=DOWN;
|
||||||
|
LOCATE COMP "gpio_12" SITE "H2";
|
||||||
|
IOBUF PORT "gpio_12" IO_TYPE=LVCMOS33;
|
||||||
|
IOBUF PORT "gpio_12" PULLMODE=DOWN;
|
||||||
|
LOCATE COMP "gpio_13" SITE "J2";
|
||||||
|
IOBUF PORT "gpio_13" IO_TYPE=LVCMOS33;
|
||||||
|
IOBUF PORT "gpio_13" PULLMODE=DOWN;
|
||||||
|
LOCATE COMP "gpio_a0" SITE "L4";
|
||||||
|
IOBUF PORT "gpio_a0" IO_TYPE=LVCMOS33;
|
||||||
|
IOBUF PORT "gpio_a0" PULLMODE=DOWN;
|
||||||
|
LOCATE COMP "gpio_a1" SITE "N3";
|
||||||
|
IOBUF PORT "gpio_a1" IO_TYPE=LVCMOS33;
|
||||||
|
IOBUF PORT "gpio_a1" PULLMODE=DOWN;
|
||||||
|
LOCATE COMP "gpio_a2" SITE "N4";
|
||||||
|
IOBUF PORT "gpio_a2" IO_TYPE=LVCMOS33;
|
||||||
|
IOBUF PORT "gpio_a2" PULLMODE=DOWN;
|
||||||
|
LOCATE COMP "gpio_a3" SITE "H4";
|
||||||
|
IOBUF PORT "gpio_a3" IO_TYPE=LVCMOS33;
|
||||||
|
IOBUF PORT "gpio_a3" PULLMODE=DOWN;
|
||||||
|
LOCATE COMP "usr_btn" SITE "J17";
|
||||||
|
IOBUF PORT "usr_btn" IO_TYPE=SSTL135_I;
|
||||||
|
LOCATE COMP "rst_n" SITE "V17";
|
||||||
|
IOBUF PORT "rst_n" IO_TYPE=LVCMOS33;
|
||||||
|
LOCATE COMP "spiflash4x_cs_n" SITE "U17";
|
||||||
|
IOBUF PORT "spiflash4x_cs_n" IO_TYPE=LVCMOS33;
|
||||||
|
LOCATE COMP "spiflash4x_dq[0]" SITE "U18";
|
||||||
|
IOBUF PORT "spiflash4x_dq[0]" IO_TYPE=LVCMOS33;
|
||||||
|
LOCATE COMP "spiflash4x_dq[1]" SITE "T18";
|
||||||
|
IOBUF PORT "spiflash4x_dq[1]" IO_TYPE=LVCMOS33;
|
||||||
|
LOCATE COMP "spiflash4x_dq[2]" SITE "R18";
|
||||||
|
IOBUF PORT "spiflash4x_dq[2]" IO_TYPE=LVCMOS33;
|
||||||
|
LOCATE COMP "spiflash4x_dq[3]" SITE "N18";
|
||||||
|
IOBUF PORT "spiflash4x_dq[3]" IO_TYPE=LVCMOS33;
|
||||||
|
LOCATE COMP "usb_d_p" SITE "N1";
|
||||||
|
IOBUF PORT "usb_d_p" IO_TYPE=LVCMOS33;
|
||||||
|
LOCATE COMP "usb_d_n" SITE "M2";
|
||||||
|
IOBUF PORT "usb_d_n" IO_TYPE=LVCMOS33;
|
||||||
|
LOCATE COMP "usb_pullup" SITE "N2";
|
||||||
|
IOBUF PORT "usb_pullup" IO_TYPE=LVCMOS33;
|
||||||
@ -25,12 +25,17 @@ module doublemem(input [19:0] address,inout wire [15:0] data ,input rd,input wr,
|
|||||||
reg [15:0] memory [0:32768];
|
reg [15:0] memory [0:32768];
|
||||||
|
|
||||||
initial begin
|
initial begin
|
||||||
|
`ifndef YOSYS
|
||||||
string boot_code;
|
string boot_code;
|
||||||
if(!$value$plusargs("BOOT_CODE=%s",boot_code))begin
|
if(!$value$plusargs("BOOT_CODE=%s",boot_code))begin
|
||||||
$display("No boot code specified. Please add +BOOT_CODE=<path> to your vvp args");
|
$display("No boot code specified. Please add +BOOT_CODE=<path> to your vvp args");
|
||||||
$finish;
|
$finish;
|
||||||
end
|
end
|
||||||
$readmemh(boot_code, memory,0,32767);
|
$readmemh(boot_code, memory,0,32767);
|
||||||
|
`else
|
||||||
|
//TODO: don't have it hard coded
|
||||||
|
$readmemh("boot_code.txt", memory,0,32767);
|
||||||
|
`endif
|
||||||
end
|
end
|
||||||
|
|
||||||
assign data[7:0] = !address[0:0] & !rd & !cs ? memory[address[16:1]][15:8] : 8'hz;
|
assign data[7:0] = !address[0:0] & !rd & !cs ? memory[address[16:1]][15:8] : 8'hz;
|
||||||
|
|||||||
@ -20,6 +20,7 @@
|
|||||||
`include "exec_state_def.v"
|
`include "exec_state_def.v"
|
||||||
`include "alu_header.v"
|
`include "alu_header.v"
|
||||||
`include "config.v"
|
`include "config.v"
|
||||||
|
`include "error_header.v"
|
||||||
|
|
||||||
//HALT: active high
|
//HALT: active high
|
||||||
//IOMEM: 1=IO 0=MEM
|
//IOMEM: 1=IO 0=MEM
|
||||||
|
|||||||
@ -50,8 +50,13 @@ doublemem sysmem(address_bus,data_bus,rd,wr,BHE,IOMEM);
|
|||||||
string stats_name,version,commit;
|
string stats_name,version,commit;
|
||||||
integer json_file_descriptor;
|
integer json_file_descriptor;
|
||||||
`endif
|
`endif
|
||||||
|
|
||||||
|
`ifndef YOSYS
|
||||||
string waveform_name;
|
string waveform_name;
|
||||||
|
`endif
|
||||||
|
|
||||||
initial begin
|
initial begin
|
||||||
|
`ifndef YOSYS
|
||||||
if($value$plusargs("WAVEFORM=%s",waveform_name))begin
|
if($value$plusargs("WAVEFORM=%s",waveform_name))begin
|
||||||
$dumpfile(waveform_name);
|
$dumpfile(waveform_name);
|
||||||
$dumpvars(0,p,cycles);
|
$dumpvars(0,p,cycles);
|
||||||
@ -66,6 +71,7 @@ initial begin
|
|||||||
end else
|
end else
|
||||||
json_file_descriptor=0;
|
json_file_descriptor=0;
|
||||||
`endif
|
`endif
|
||||||
|
`endif
|
||||||
sane=0;
|
sane=0;
|
||||||
finish=0;
|
finish=0;
|
||||||
end
|
end
|
||||||
@ -105,11 +111,16 @@ end
|
|||||||
`endif
|
`endif
|
||||||
|
|
||||||
reg [1:0] finish;
|
reg [1:0] finish;
|
||||||
|
|
||||||
|
`ifndef YOSYS
|
||||||
string memdump_name;
|
string memdump_name;
|
||||||
|
`endif
|
||||||
always @(posedge HALT) begin
|
always @(posedge HALT) begin
|
||||||
|
`ifndef YOSYS
|
||||||
if($value$plusargs("MEMDUMP=%s",memdump_name))begin
|
if($value$plusargs("MEMDUMP=%s",memdump_name))begin
|
||||||
$writememh(memdump_name, sysmem.memory,0,32767);
|
$writememh(memdump_name, sysmem.memory,0,32767);
|
||||||
end
|
end
|
||||||
|
`endif
|
||||||
finish<=2'd1;
|
finish<=2'd1;
|
||||||
end
|
end
|
||||||
|
|
||||||
@ -140,7 +151,11 @@ always @(posedge clock) begin
|
|||||||
$fdisplay(json_file_descriptor,"],\n\"Total Cycles\":%0d,\n\"Instructions run\":%0d\n}",cycles-1,instruction_count_temp);
|
$fdisplay(json_file_descriptor,"],\n\"Total Cycles\":%0d,\n\"Instructions run\":%0d\n}",cycles-1,instruction_count_temp);
|
||||||
`endif
|
`endif
|
||||||
end
|
end
|
||||||
2'd3: $finish;
|
2'd3: begin
|
||||||
|
`ifndef SYNTHESIS
|
||||||
|
$finish;
|
||||||
|
`endif
|
||||||
|
end
|
||||||
endcase
|
endcase
|
||||||
end
|
end
|
||||||
|
|
||||||
@ -162,9 +177,11 @@ always @( ERROR ) begin
|
|||||||
end
|
end
|
||||||
endcase
|
endcase
|
||||||
$display("Cycles run for: %0d",cycles-1);
|
$display("Cycles run for: %0d",cycles-1);
|
||||||
|
`ifndef SYNTHESIS
|
||||||
if($value$plusargs("MEMDUMP=%s",memdump_name))begin
|
if($value$plusargs("MEMDUMP=%s",memdump_name))begin
|
||||||
$writememh(memdump_name, system.sysmem.memory,0,32767);
|
$writememh(memdump_name, system.sysmem.memory,0,32767);
|
||||||
end
|
end
|
||||||
|
`endif
|
||||||
finish<=2'd1;
|
finish<=2'd1;
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
|
|||||||
Loading…
Reference in New Issue
Block a user