Fixed ADD again and some memory read logic. Compiler runs the default brainfuck message program!!
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@ -110,7 +110,7 @@ always @( CIR or SIMPLE_MICRO or seq_addr_input ) begin
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/* ADD - Add Immediate word/byte to register/memory */
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/* 1 0 0 0 0 0 S W | MOD 0 0 0 R/M | < DISP LO > | < DISP HI > | DATA | DATA if W | */
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/* SUB - Subtract mmediate word/byte from register/memory */
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/* 1 0 0 0 0 0 S W | MOD 0 0 0 R/M | < DISP LO > | < DISP HI > | DATA | DATA if W | */
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/* 1 0 0 0 0 0 S W | MOD 1 0 1 R/M | < DISP LO > | < DISP HI > | DATA | DATA if W | */
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opcode_size=1;
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has_operands=1;
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Wbit=CIR[8:8];
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@ -118,10 +118,14 @@ always @( CIR or SIMPLE_MICRO or seq_addr_input ) begin
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IN_MOD=CIR[7:6];
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RM=CIR[2:0];
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in_alu1_sel1=2'b00;
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if(IN_MOD==2'b11)begin
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in_alu1_sel2=2'b01;
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OUT_MOD={1'b0,IN_MOD};
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reg_read_port2_addr={Wbit,RM};
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reg_write_addr={Wbit,RM};
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end else begin
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in_alu1_sel2=2'b00;
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end
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OUT_MOD={1'b0,IN_MOD};
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case({Sbit,Wbit})
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2'b00,2'b11:begin
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`start_unaligning_instruction
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@ -305,7 +305,10 @@ always @(negedge clock) begin
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end else begin
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PARAM1[7:0] = external_data_bus[15:8];
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end
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state=`PROC_EX_STATE_ENTRY;
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case(IN_MOD)
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3'b000,3'b001,3'b010: state=`PROC_MEMIO_READ;
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default: state=`PROC_EX_STATE_ENTRY;
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endcase
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end
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default:begin
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end
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@ -385,7 +388,10 @@ always @(posedge clock) begin
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end else begin
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PARAM1[7:0] = CIR[7:0];
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end
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state=`PROC_EX_STATE_ENTRY;
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case(IN_MOD)
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3'b000,3'b001,3'b010: state=`PROC_MEMIO_READ;
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default: state=`PROC_EX_STATE_ENTRY;
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endcase
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end else begin
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if(unaligned_access==1)begin
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if({Sbit,Wbit}==2'b11)begin
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@ -395,7 +401,10 @@ always @(posedge clock) begin
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PARAM1[7:0] = external_data_bus[7:0];
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end
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ProgCount=ProgCount+1;
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state=`PROC_EX_STATE_ENTRY;
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case(IN_MOD)
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3'b000,3'b001,3'b010: state=`PROC_MEMIO_READ;
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default: state=`PROC_EX_STATE_ENTRY;
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endcase
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end else begin
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external_address_bus=ProgCount;
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state=`PROC_DE_LOAD_8_PARAM_UNALIGNED;
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