diff --git a/system/decoder.v b/system/decoder.v
index 1967f7a..f6c042d 100644
--- a/system/decoder.v
+++ b/system/decoder.v
@@ -110,7 +110,7 @@ always @( CIR or SIMPLE_MICRO or seq_addr_input ) begin
 				/*                                  ADD - Add Immediate word/byte to register/memory                                      */
 				/* 1 0 0 0  0 0 S W | MOD 0 0  0  R/M  |     < DISP LO >  |     < DISP HI >   |      DATA        |      DATA if W    |    */
 				/*                                  SUB - Subtract mmediate word/byte from register/memory                                */
-				/* 1 0 0 0  0 0 S W | MOD 0 0  0  R/M  |     < DISP LO >  |     < DISP HI >   |      DATA        |      DATA if W    |    */
+				/* 1 0 0 0  0 0 S W | MOD 1 0  1  R/M  |     < DISP LO >  |     < DISP HI >   |      DATA        |      DATA if W    |    */
 				opcode_size=1;
 				has_operands=1;
 				Wbit=CIR[8:8];
@@ -118,10 +118,14 @@ always @( CIR or SIMPLE_MICRO or seq_addr_input ) begin
 				IN_MOD=CIR[7:6];
 				RM=CIR[2:0];
 				in_alu1_sel1=2'b00;
-				in_alu1_sel2=2'b01;
+				if(IN_MOD==2'b11)begin
+					in_alu1_sel2=2'b01;
+					reg_read_port2_addr={Wbit,RM};
+					reg_write_addr={Wbit,RM};
+				end else begin
+					in_alu1_sel2=2'b00;
+				end
 				OUT_MOD={1'b0,IN_MOD};
-				reg_read_port2_addr={Wbit,RM};
-				reg_write_addr={Wbit,RM};
 				case({Sbit,Wbit})
 					2'b00,2'b11:begin
 						`start_unaligning_instruction
diff --git a/system/processor.v b/system/processor.v
index c1c2f0a..b64af9d 100644
--- a/system/processor.v
+++ b/system/processor.v
@@ -305,7 +305,10 @@ always @(negedge clock) begin
 				end else begin
 					PARAM1[7:0] = external_data_bus[15:8];
 				end
-				state=`PROC_EX_STATE_ENTRY;
+				case(IN_MOD)
+					3'b000,3'b001,3'b010: state=`PROC_MEMIO_READ;
+					default:              state=`PROC_EX_STATE_ENTRY;
+				endcase
 		end
 		default:begin
 		end
@@ -385,7 +388,10 @@ always @(posedge clock) begin
 				end else begin
 					PARAM1[7:0] = CIR[7:0];
 				end
-				state=`PROC_EX_STATE_ENTRY;
+				case(IN_MOD)
+					3'b000,3'b001,3'b010: state=`PROC_MEMIO_READ;
+					default:              state=`PROC_EX_STATE_ENTRY;
+				endcase
 			end else begin
 				if(unaligned_access==1)begin
 					if({Sbit,Wbit}==2'b11)begin
@@ -395,7 +401,10 @@ always @(posedge clock) begin
 						PARAM1[7:0] = external_data_bus[7:0];
 					end
 					ProgCount=ProgCount+1;
-					state=`PROC_EX_STATE_ENTRY;
+					case(IN_MOD)
+						3'b000,3'b001,3'b010: state=`PROC_MEMIO_READ;
+						default:              state=`PROC_EX_STATE_ENTRY;
+					endcase
 				end else begin
 					external_address_bus=ProgCount;
 					state=`PROC_DE_LOAD_8_PARAM_UNALIGNED;