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Fixed ADD again and some memory read logic. Compiler runs the default brainfuck message program!!

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(Tim) Efthimis Kritikos 2023-02-24 14:09:10 +00:00
parent 3e484a0ceb
commit 5af6d720c3
2 changed files with 20 additions and 7 deletions
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8
system/decoder.v
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@ -110,7 +110,7 @@ always @( CIR or SIMPLE_MICRO or seq_addr_input ) begin
/* ADD - Add Immediate word/byte to register/memory */ /* ADD - Add Immediate word/byte to register/memory */
/* 1 0 0 0 0 0 S W | MOD 0 0 0 R/M | < DISP LO > | < DISP HI > | DATA | DATA if W | */ /* 1 0 0 0 0 0 S W | MOD 0 0 0 R/M | < DISP LO > | < DISP HI > | DATA | DATA if W | */
/* SUB - Subtract mmediate word/byte from register/memory */ /* SUB - Subtract mmediate word/byte from register/memory */
/* 1 0 0 0 0 0 S W | MOD 0 0 0 R/M | < DISP LO > | < DISP HI > | DATA | DATA if W | */ /* 1 0 0 0 0 0 S W | MOD 1 0 1 R/M | < DISP LO > | < DISP HI > | DATA | DATA if W | */
opcode_size=1; opcode_size=1;
has_operands=1; has_operands=1;
Wbit=CIR[8:8]; Wbit=CIR[8:8];
@ -118,10 +118,14 @@ always @( CIR or SIMPLE_MICRO or seq_addr_input ) begin
IN_MOD=CIR[7:6]; IN_MOD=CIR[7:6];
RM=CIR[2:0]; RM=CIR[2:0];
in_alu1_sel1=2'b00; in_alu1_sel1=2'b00;
if(IN_MOD==2'b11)begin
in_alu1_sel2=2'b01; in_alu1_sel2=2'b01;
OUT_MOD={1'b0,IN_MOD};
reg_read_port2_addr={Wbit,RM}; reg_read_port2_addr={Wbit,RM};
reg_write_addr={Wbit,RM}; reg_write_addr={Wbit,RM};
end else begin
in_alu1_sel2=2'b00;
end
OUT_MOD={1'b0,IN_MOD};
case({Sbit,Wbit}) case({Sbit,Wbit})
2'b00,2'b11:begin 2'b00,2'b11:begin
`start_unaligning_instruction `start_unaligning_instruction

15
system/processor.v
View File

@ -305,7 +305,10 @@ always @(negedge clock) begin
end else begin end else begin
PARAM1[7:0] = external_data_bus[15:8]; PARAM1[7:0] = external_data_bus[15:8];
end end
state=`PROC_EX_STATE_ENTRY; case(IN_MOD)
3'b000,3'b001,3'b010: state=`PROC_MEMIO_READ;
default: state=`PROC_EX_STATE_ENTRY;
endcase
end end
default:begin default:begin
end end
@ -385,7 +388,10 @@ always @(posedge clock) begin
end else begin end else begin
PARAM1[7:0] = CIR[7:0]; PARAM1[7:0] = CIR[7:0];
end end
state=`PROC_EX_STATE_ENTRY; case(IN_MOD)
3'b000,3'b001,3'b010: state=`PROC_MEMIO_READ;
default: state=`PROC_EX_STATE_ENTRY;
endcase
end else begin end else begin
if(unaligned_access==1)begin if(unaligned_access==1)begin
if({Sbit,Wbit}==2'b11)begin if({Sbit,Wbit}==2'b11)begin
@ -395,7 +401,10 @@ always @(posedge clock) begin
PARAM1[7:0] = external_data_bus[7:0]; PARAM1[7:0] = external_data_bus[7:0];
end end
ProgCount=ProgCount+1; ProgCount=ProgCount+1;
state=`PROC_EX_STATE_ENTRY; case(IN_MOD)
3'b000,3'b001,3'b010: state=`PROC_MEMIO_READ;
default: state=`PROC_EX_STATE_ENTRY;
endcase
end else begin end else begin
external_address_bus=ProgCount; external_address_bus=ProgCount;
state=`PROC_DE_LOAD_8_PARAM_UNALIGNED; state=`PROC_DE_LOAD_8_PARAM_UNALIGNED;