From 4767a7addcfb490c21836fd8b284db8cf0f22bb8 Mon Sep 17 00:00:00 2001 From: "(Tim) Efthimis Kritikos" Date: Mon, 6 Nov 2023 08:18:19 +0000 Subject: [PATCH] Updated progress on README --- README.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/README.md b/README.md index c8d85f0..6952fc6 100644 --- a/README.md +++ b/README.md @@ -13,7 +13,7 @@ A CPU that aims to be binary compatible with the 8086 ISA, focused on optimisati * [X] Is pipelined * [ ] Is Out of Order * [ ] Is superscalar - * [ ] Has been successfully synthesized + * [X] Has been successfully synthesized ### Simulating it Both Verilator and Icarus Verilog can be used for simulation. You can select which one you want with the SIM variable on [common.mk](./common.mk)