Lots of cleanup mainly on processor.v
This commit is contained in:
parent
a693b87e96
commit
42c319d55d
@ -1,15 +1,15 @@
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[*]
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[*] GTKWave Analyzer v3.3.111 (w)1999-2020 BSI
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[*] Tue May 16 18:44:13 2023
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[*] Wed May 31 20:14:37 2023
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[*]
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[dumpfile] "/home/user/9086/system/boot_code.fst"
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[dumpfile_mtime] "Tue May 16 18:40:53 2023"
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[dumpfile_size] 205398
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[dumpfile_mtime] "Wed May 31 20:14:23 2023"
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[dumpfile_size] 4718
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[savefile] "/home/user/9086/gtkwave_savefile.gtkw"
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[timestart] 24360000000
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[size] 1140 1003
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[timestart] 500000000
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[size] 1044 1003
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[pos] -1 -1
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*-33.095047 38460000000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
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*-32.495049 38460000000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
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[treeopen] TOP.
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[treeopen] TOP.system.
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[treeopen] TOP.system.p.
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@ -33,22 +33,16 @@ TOP.system.p.write
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-
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@28
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TOP.system.p.BIU.VALID_INSTRUCTION
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TOP.system.p.valid_instruction_ack
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TOP.system.p.valid_exec_data
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@29
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TOP.system.p.execute_unit.next_exec
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@23
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TOP.system.p.IF2DE_INSTRUCTION[31:0]
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@22
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TOP.system.p.execute_unit.INSTRUCTION_BUFFER[23:0]
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TOP.system.p.BIU.biu_state[3:0]
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@28
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TOP.system.p.execute_unit.exec_state[3:0]
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TOP.system.p.proc_state[2:0]
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TOP.system.p.BIU.write_request
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TOP.system.p.BIU.read_request
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TOP.system.p.SIMPLE_MICRO
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@22
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TOP.system.p.ucode_seq_addr[4:0]
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@28
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TOP.system.p.execute_unit.biu_jump_req
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@200
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-
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@ -58,7 +52,6 @@ TOP.system.IOMEM
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TOP.system.p.HALT
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@22
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TOP.system.p.BIU.INSTRUCTION[31:0]
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TOP.system.p.decoder.seq_addr_entry[4:0]
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TOP.system.p.BIU.FIFO_end[3:0]
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TOP.system.p.BIU.FIFO_start[3:0]
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TOP.system.p.BIU.INPUT_FIFO[0][7:0]
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39
system/biu.v
39
system/biu.v
@ -38,14 +38,33 @@
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`define BIU_GET_SECOND_BYTE1 4'b1110
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module BIU (
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/* Outside world */ input clock, input reset, output reg [19:0] external_address_bus,
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/* */ inout [15:0] external_data_bus,output reg read, output reg write,output reg BHE,output reg IOMEM,
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/* Internal */ output reg [31:0] INSTRUCTION, output reg VALID_INSTRUCTION, output reg [15:0] INSTRUCTION_LOCATION, input jump_req,
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/* */ input[15:0] ADDRESS_INPUT, inout [15:0] DATA, input write_request, input read_request, input Wbit, output reg VALID_DATA, input MEM_OR_IO,
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/* */ input valid_instruction_ack
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/***************** GENERAL *****************/
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/* */ input clock, input reset
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/**************** OUTSIDE WORLD ****************/
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/* */ ,output reg [19:0] external_address_bus
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/* */ ,inout [15:0] external_data_bus,output reg read, output reg write,output reg BHE,output reg IOMEM
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/**************** OUTPUT TO DE ****************/
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/* */ ,output reg [31:0] INSTRUCTION, output reg VALID_INSTRUCTION, output reg [15:0] INSTRUCTION_LOCATION
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/* */ ,output reg VALID_DATA, output reg DATA_DIR
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/**************** INPUT FROM DE ****************/
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,input Wbit, input MEM_OR_IO, input valid_instruction_ack
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/**************** INPUT FROM EX ****************/
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/* */ ,input jump_req, input write_request, input read_request
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/* */ ,input[15:0] ADDRESS_INPUT
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/************ BIDIRECTIONAL WITH EX ************/
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/* */ ,inout [15:0] DATA
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`ifdef OTUPUT_JSON_STATISTICS
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/* Statistics */ ,output wire [`L1_CACHE_SIZE-1:0] FIFO_SIZE_STAT, output wire VALID_INSTRUCTION_STAT
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/***************** STATISTICS *****************/
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/* */ ,output wire [`L1_CACHE_SIZE-1:0] FIFO_SIZE_STAT, output wire VALID_INSTRUCTION_STAT
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`endif
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);
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`ifdef OTUPUT_JSON_STATISTICS
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@ -57,7 +76,6 @@ reg [15:0] data_bus_output_register;
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assign external_data_bus=read?data_bus_output_register:16'hz;
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reg [15:0] DATA_OUT;
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reg DATA_DIR;
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assign DATA=DATA_DIR ? 16'hz:DATA_OUT;
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`define FIFO_SIZE_BYTES $rtoi($pow(2,`L1_CACHE_SIZE))
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@ -75,6 +93,10 @@ always @(negedge reset) begin
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end
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always @(posedge reset) begin
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biu_state <= `BIU_RESET;
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/* verilator lint_off BLKSEQ */
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FIFO_start = `L1_CACHE_SIZE'b0;
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/* verilator lint_on BLKSEQ */
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FIFO_end <= `L1_CACHE_SIZE'b0;
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end
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reg jump_req_latch;
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@ -318,6 +340,7 @@ InstrSize fifoInstrSize2(
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always @( valid_instruction_ack ) begin
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/* verilator lint_off BLKSEQ */
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FIFO_start = FIFO_start + {{`L1_CACHE_SIZE-3{1'b0}},Isize};
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/* verilator lint_on BLKSEQ */
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INSTRUCTION_LOCATION <= INSTRUCTION_LOCATION + {13'd0,Isize};
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`ifdef DOUBLE_INSTRUCTION_LOAD
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if(FIFO_SIZE>`L1_CACHE_SIZE'd3+{{`L1_CACHE_SIZE-3{1'b0}},Isize})begin
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@ -340,7 +363,6 @@ always @( valid_instruction_ack ) begin
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VALID_INSTRUCTION <= 0;
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end else begin
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VALID_INSTRUCTION <= 0;
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/* verilator lint_on BLKSEQ */
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end
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`else
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VALID_INSTRUCTION <= 0;
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@ -349,6 +371,7 @@ end
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always @( posedge jump_req ) begin
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jump_req_latch <= 1;
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DATA_DIR <= 1;
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VALID_INSTRUCTION <= 0;
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end
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180
system/decoder.v
180
system/decoder.v
@ -24,33 +24,69 @@
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`include "config.v"
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`define DE_STATE_BITS 2
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`define DE_RESET 2'b00
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`define DE_STATE_ENTRY 2'b01
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`define DE_HALT 2'b10
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module decoder(
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/* GENERAL */ input clock, input reset
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/* INPUT FROM IF */ ,input wire [31:0] IF2DE_INSTRUCTION,input wire VALID_INSTRUCTION, input [15:0] INSTRUCTION_LOCATION
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/* INPUT FROM EX */ ,input wire [7:0] EX2DE_FLAGS,input wire next_exec
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/* OUTPUT TO EX */ ,output reg [`EXEC_STATE_BITS+`ERROR_BITS+65:0] DE_OUTPUT_sampled
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/* */ ,output reg [15:0] ProgCount, output reg set_initial_values,output reg valid_exec_data
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/***************** GENERAL *****************/
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/* Input from sys. */ input clock, input reset
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/* Output to sys. */ ,output reg MEM_OR_IO_LATCHED, output reg [`ERROR_BITS-1:0] ERROR_LATCHED, output reg HALT_LATCHED
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/*************** INPUT FROM IF ***************/
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/* */ ,input wire [31:0] IF2DE_INSTRUCTION, input wire VALID_INSTRUCTION
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/* */ ,input wire [15:0] INSTRUCTION_LOCATION
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/*************** OUTPUT TO IF ***************/
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/* OUTPUT TO IF */ ,output reg VALID_INSTRUCTION_ACK
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/*************** INPUT FROM EX ***************/
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/* */ ,input wire [7:0] EX2DE_FLAGS,input wire next_exec
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/*************** OUTPUT TO DE ***************/
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/* SYNC SIGNALS */ ,output reg set_initial_values, output reg valid_exec_data
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/* INSTR. PARAMS */ ,output reg Wbit_LATCHED, output reg [2:0] IN_MOD_LATCHED, output reg [2:0] OUT_MOD_LATCHED, output reg [2:0] RM_LATCHED
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/* DATA */ ,output reg [15:0] PARAM1_LATCHED, output reg [15:0] PARAM2_LATCHED,output reg [15:0] ProgCount
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/* STATE CONTROL */ ,output reg [`EXEC_STATE_BITS-1:0] next_state_LATCHED
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/* ALU CONTROL */ ,output reg [1:0] in_alu_sel1_LATCHED, output reg [1:0] in_alu_sel2_LATCHED,output reg [2:0] ALU_OP_LATCHED
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/* OTHER */ ,output reg memio_address_select_LATCHED
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/************* OUTPUT TO REGISTERS ************/
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/* */ ,output reg [3:0] reg_write_addr_LATCHED, output reg [3:0] reg_read_port2_addr_LATCHED, output reg [3:0] reg_read_port1_addr_LATCHED
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`ifdef CALCULATE_IPC
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/* STATISTICS */ ,output reg new_instruction
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`endif
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);
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reg SIMPLE_MICRO; /* use simple decodings (=0) or microcode data (=1) */
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wire [`UCODE_ADDR_BITS-1:0] ucode_seq_addr_entry;
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reg [`UCODE_ADDR_BITS-1:0] ucode_seq_addr;
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wire DEPENDS_ON_PREVIOUS;
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wire [`EXEC_STATE_BITS+`ERROR_BITS+65:0] DE_OUTPUT;
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wire set_params;
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wire MEM_OR_IO, HALT,Wbit,memio_address_select;
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wire [1:0] in_alu_sel1,in_alu_sel2;
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wire [2:0] IN_MOD,OUT_MOD,RM,ALU_OP;
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wire [3:0] reg_write_addr,reg_read_port2_addr,reg_read_port1_addr;
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wire [15:0] PARAM1,PARAM2;
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wire [`EXEC_STATE_BITS-1:0] next_state;
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wire [`ERROR_BITS-1:0] ERROR;
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instruction_decode instruction_decode(
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/* INPUT */ IF2DE_INSTRUCTION,{8'h0,EX2DE_FLAGS},
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/* MICROCODE */ ucode_seq_addr_entry,SIMPLE_MICRO,ucode_seq_addr,
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/* OUTPUT */ DE_OUTPUT,DEPENDS_ON_PREVIOUS, set_params
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/* INPUT */ IF2DE_INSTRUCTION,{8'h0,EX2DE_FLAGS}
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/* MICROCODE */ ,ucode_seq_addr_entry,SIMPLE_MICRO,ucode_seq_addr
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/* OUTPUT */ ,DEPENDS_ON_PREVIOUS, set_params, MEM_OR_IO,ERROR, HALT
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/*************** INPUT FROM DE ***************/
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/* INSTR. PARAMS */ ,Wbit, IN_MOD, OUT_MOD, RM
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/* DATA */ ,PARAM1, PARAM2
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/* STATE CONTROL */ ,next_state
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/* ALU CONTROL */ ,in_alu_sel1,in_alu_sel2, ALU_OP
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/* OTHER */ ,memio_address_select
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/***************** REGISTERS *****************/
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/* */ ,reg_write_addr, reg_read_port2_addr, reg_read_port1_addr
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);
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reg [`DE_STATE_BITS-1:0] de_state;
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@ -61,15 +97,25 @@ always @(negedge reset) begin
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`ifdef CALCULATE_IPC
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new_instruction<=0;
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`endif
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end
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always @(posedge reset) begin
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de_state <= `DE_RESET;
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/* need early init */
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VALID_INSTRUCTION_ACK <= 0;
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valid_exec_data<=0;
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instant_response <= 0;
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stalled_response <= 0;
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end
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always @(posedge reset) begin
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de_state <= `DE_STATE_ENTRY;
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/* need early init */
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ucode_seq_addr <= `UCODE_NO_INSTRUCTION;
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SIMPLE_MICRO <= 0;
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owe_set_init <= 0;
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set_initial_values<=0;
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wait_exec<=0;
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first_ucode <= 0;
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HALT_LATCHED <= 0;
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ERROR_LATCHED <= `ERROR_BITS'h0;
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VALID_INSTRUCTION_ACK <= 0;
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end
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wire [2:0] instr_end;
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InstrSize InstrSize({IF2DE_INSTRUCTION[31:24],IF2DE_INSTRUCTION[21:19]},instr_end);
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@ -96,8 +142,24 @@ end
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reg first_ucode;
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always @(instant_response or stalled_response) begin
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DE_OUTPUT_sampled <= DE_OUTPUT;
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//`define LATCH(VAR) VAR_LATCHED <= VAR; //TODO would this work?
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IN_MOD_LATCHED <= IN_MOD;
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OUT_MOD_LATCHED <= OUT_MOD;
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RM_LATCHED <= RM;
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MEM_OR_IO_LATCHED <= MEM_OR_IO;
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PARAM1_LATCHED <= PARAM1;
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PARAM2_LATCHED <= PARAM2;
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ALU_OP_LATCHED <= ALU_OP;
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in_alu_sel1_LATCHED <= in_alu_sel1;
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in_alu_sel2_LATCHED <= in_alu_sel2;
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reg_read_port1_addr_LATCHED <= reg_read_port1_addr;
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reg_read_port2_addr_LATCHED <= reg_read_port2_addr;
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reg_write_addr_LATCHED <= reg_write_addr;
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Wbit_LATCHED <= Wbit;
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ERROR_LATCHED <= ERROR;
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HALT_LATCHED <= HALT;
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next_state_LATCHED <= next_state;
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memio_address_select_LATCHED <= memio_address_select;
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if ( (ucode_seq_addr==`UCODE_NO_INSTRUCTION) && (ucode_seq_addr_entry!=`UCODE_NO_INSTRUCTION) )begin
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/* switch to microcode decoding */
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@ -138,17 +200,6 @@ end
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always @(posedge clock) begin
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case(de_state)
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`DE_RESET:begin
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ucode_seq_addr <= `UCODE_NO_INSTRUCTION;
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DE_OUTPUT_sampled <= 0;
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SIMPLE_MICRO <= 0;
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de_state <= `DE_STATE_ENTRY;
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owe_set_init <= 0;
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set_initial_values<=0;
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wait_exec<=0;
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valid_exec_data<=0;
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first_ucode <= 0;
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end
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`DE_STATE_ENTRY:begin
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if ( ( VALID_INSTRUCTION==1 || SIMPLE_MICRO == 1 ) && wait_exec==0) begin
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stalled_response <= !stalled_response;
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@ -164,12 +215,12 @@ end
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endmodule
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/************************ Instruction specific decoding **********************************/
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///////////////////////// Instruction specific decoding ///////////////////////////////////
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module microcode(
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input [`UCODE_ADDR_BITS-1:0] ADDR,
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output [`UCODE_DATA_BITS-1:0] DATA
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input [`UCODE_ADDR_BITS-1:0] ADDR
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,output [`UCODE_DATA_BITS-1:0] DATA
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);
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initial begin
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@ -191,62 +242,23 @@ endmodule
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module instruction_decode(
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/* INPUTS */ input wire [31:0] INSTRUCTION,input wire [15:0] FLAGS
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/* MICROCODE */ ,output reg [`UCODE_ADDR_BITS-1:0] seq_addr_entry, input wire SIMPLE_MICRO, input wire [`UCODE_ADDR_BITS-1:0] seq_addr_input
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/* OUTPUT */ ,output wire [`EXEC_STATE_BITS+`ERROR_BITS+65:0] OUTPUT, output reg DEPENDS_ON_PREVIOUS, output reg set_params
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/* OUTPUT */ ,output reg DEPENDS_ON_PREVIOUS, output reg set_params,output reg MEM_OR_IO, output reg [`ERROR_BITS-1:0] ERROR, output reg HALT
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/*************** INPUT FROM DE ***************/
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/* INSTR. PARAMS */ ,output reg Wbit, output reg [2:0] IN_MOD, output reg [2:0] OUT_MOD, output reg [2:0] RM
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/* DATA */ ,output reg [15:0] PARAM1, output reg [15:0] PARAM2
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/* STATE CONTROL */ ,output reg [`EXEC_STATE_BITS-1:0] next_state
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/* ALU CONTROL */ ,output reg [1:0] in_alu_sel1, output reg [1:0] in_alu_sel2,output reg [2:0] ALU_OP
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/* OTHER */ ,output reg memio_address_select
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/***************** REGISTERS *****************/
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/* */ ,output reg [3:0] reg_write_addr, output reg [3:0] reg_read_port2_addr, output reg [3:0] reg_read_port1_addr
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);
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/* DEPENDS_ON_PREVIOUS - This encodes weather the instruction requires the previous to be finished in order to be decoded. This, for example, affects
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* conditional jumps since flags are checked during decode.
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*/
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reg [2:0]IN_MOD;
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assign OUTPUT[2:0] = IN_MOD;
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reg [2:0]RM;
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assign OUTPUT[5:3] = RM;
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reg memio_address_select;
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assign OUTPUT[6:6] = memio_address_select;
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reg MEM_OR_IO;
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assign OUTPUT[7:7] = MEM_OR_IO;
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reg [15:0] PARAM1;
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assign OUTPUT[23:8] = PARAM1;
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reg [15:0] PARAM2;
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assign OUTPUT[39:24] = PARAM2;
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reg [2:0]ALU_OP;
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assign OUTPUT[42:40] = ALU_OP;
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reg [1:0]in_alu_sel1;
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assign OUTPUT[44:43] = in_alu_sel1;
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reg [1:0]in_alu_sel2;
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assign OUTPUT[46:45] = in_alu_sel2;
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reg [2:0]OUT_MOD;
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assign OUTPUT[49:47] = OUT_MOD;
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reg [3:0]reg_read_port1_addr;
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assign OUTPUT[53:50] = reg_read_port1_addr;
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reg [3:0]reg_read_port2_addr;
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assign OUTPUT[57:54] = reg_read_port2_addr;
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reg [3:0]reg_write_addr;
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assign OUTPUT[61:58] = reg_write_addr;
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reg Wbit,Sbit,opcode_size;
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assign OUTPUT[64:62] = {Wbit,Sbit,opcode_size};
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reg [`ERROR_BITS-1:0] ERROR;
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reg HALT;
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assign OUTPUT[`ERROR_BITS+65:65]={ERROR,HALT};
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reg [`EXEC_STATE_BITS-1:0] next_state;
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assign OUTPUT[`EXEC_STATE_BITS+`ERROR_BITS+65:`ERROR_BITS+66] = next_state;
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/* verilator lint_off UNUSEDSIGNAL */
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wire [`UCODE_DATA_BITS-1:0] ucode_data;
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/* verilator lint_on UNUSEDSIGNAL */
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@ -269,10 +281,12 @@ reg [1:0] PARAM_ACTION;
|
||||
`define LOAD_8 2'b01
|
||||
`define LOAD_16 2'b10
|
||||
|
||||
reg Sbit,opcode_size;
|
||||
|
||||
// I use blocking for basically putting names on the different fields of INSTRUCTION and
|
||||
// then branching off of that instead of the raw bits. otherwise the code
|
||||
// would be identical
|
||||
// verilator lint_off BLKSEQ
|
||||
/* verilator lint_off BLKSEQ */
|
||||
always @( FLAGS or INSTRUCTION or SIMPLE_MICRO or seq_addr_input ) begin
|
||||
set_params = 1;
|
||||
PARAM_ACTION = `NO_LOAD;
|
||||
@ -1009,7 +1023,7 @@ end
|
||||
`undef invalid_instruction
|
||||
|
||||
endmodule
|
||||
// verilator lint_on BLKSEQ
|
||||
/* verilator lint_on BLKSEQ */
|
||||
|
||||
|
||||
/* IN: {INSTRUCTION[31:24],INSTRUCTION[21:19]} */
|
||||
|
||||
@ -22,15 +22,34 @@
|
||||
`include "error_header.v"
|
||||
|
||||
module execute_unit (
|
||||
/* GENERAL */ input clock, input reset ,input Wbit , input valid_input
|
||||
/* */ ,input [2:0] IN_MOD, input [2:0] OUT_MOD, input memio_address_select, input [15:0] ProgCount, input [2:0] RM, output reg [`ERROR_BITS-1:0] ERROR , input write /*TODO: REMOVE!!*/
|
||||
/* */ ,input set_initial_values, output reg next_exec
|
||||
/* PARAM */ ,input [15:0] PARAM1_INIT, input [15:0] PARAM2_INIT
|
||||
/***************** GENERAL *****************/
|
||||
/* */ input clock, input reset, input write /*TODO: REMOVE!!*/, output reg [`ERROR_BITS-1:0] ERROR
|
||||
|
||||
/*************** INPUT FROM DE ***************/
|
||||
/* SYNC SIGNALS */ ,input valid_input,input set_initial_values
|
||||
/* INSTR. PARAMS */ ,input Wbit ,input [2:0] IN_MOD, input [2:0] OUT_MOD, input [2:0] RM
|
||||
/* DATA */ ,input [15:0] PARAM1_INIT, input [15:0] PARAM2_INIT, input [15:0] ProgCount
|
||||
/* STATE CONTROL */ ,input [`EXEC_STATE_BITS-1:0] init_state
|
||||
/* ALU CONTROL */ ,input [1:0] in_alu_sel1, input [1:0] in_alu_sel2, input [`ALU_OP_BITS-1:0] ALU_OP, output [15:0] _ALU_O_
|
||||
/* REGISTER DATA */ ,input [15:0] reg_read_port1_data ,input [15:0] reg_read_port2_data, output reg [3:0] reg_read_port1_addr, output reg use_exec_reg_addr, output reg reg_write_we
|
||||
/* FLAGS */ ,output reg [7:0] FLAGS
|
||||
/* BIU */ ,output reg [15:0] BIU_ADDRESS_INPUT,output reg biu_write_request, output reg biu_read_request, input BIU_VALID_DATA, input [15:0] BIU_DATA, output reg biu_data_direction, output reg biu_jump_req
|
||||
/* OTHER */ ,input memio_address_select
|
||||
|
||||
/**************** OUTPUT TO DE ****************/
|
||||
/* SYNC SIGNALS */ ,output reg next_exec
|
||||
/* FLAGS */ ,output reg [7:0] EX2DE_FLAGS
|
||||
|
||||
/**************** OUTPUT TO BIU ****************/
|
||||
/* */ ,output reg [15:0] BIU_ADDRESS_INPUT
|
||||
/* */ ,output reg biu_read_request, output reg biu_jump_req,output reg biu_write_request
|
||||
|
||||
/*************** INPUT FROM BIU ****************/
|
||||
/* */ ,input BIU_VALID_DATA, input biu_data_direction
|
||||
|
||||
/************ BIDIRECTIONAL WITH BIU ***********/
|
||||
/* */ ,inout [15:0] BIU_DATA
|
||||
|
||||
/***************** REGISTERS *****************/
|
||||
/* */ ,input [15:0] reg_read_port1_data ,input [15:0] reg_read_port2_data, output reg [3:0] reg_read_port1_addr
|
||||
/* */ ,output reg use_exec_reg_addr, output reg reg_write_we
|
||||
);
|
||||
|
||||
assign _ALU_O_ = ALU_O;
|
||||
@ -38,6 +57,8 @@ assign _ALU_O_ = ALU_O;
|
||||
reg [`EXEC_STATE_BITS-1:0] exec_state;
|
||||
reg [15:0] PARAM1,PARAM2;
|
||||
|
||||
assign BIU_DATA = biu_data_direction ? (memio_address_select ? reg_read_port1_data : ALU_O): 16'hz;
|
||||
|
||||
/*############ ALU / Execution units ################################################## */
|
||||
|
||||
mux4 #(.WIDTH(16)) MUX16_1A(
|
||||
@ -90,6 +111,7 @@ end
|
||||
|
||||
always @(posedge reset) begin
|
||||
exec_state <= `EXEC_RESET;
|
||||
next_exec <= 0;
|
||||
end
|
||||
|
||||
`define unimpl_addressing_mode exec_state <= `EXEC_WAIT;ERROR <= `ERR_UNIMPL_ADDRESSING_MODE;
|
||||
@ -101,7 +123,6 @@ always @(posedge clock) begin
|
||||
`EXEC_RESET: begin
|
||||
biu_write_request <= 0;
|
||||
biu_read_request <= 0;
|
||||
biu_data_direction <= 0;
|
||||
biu_jump_req <= 0;
|
||||
reg_write_we <= 1;
|
||||
exec_state <= `EXEC_WAIT;
|
||||
@ -111,6 +132,7 @@ always @(posedge clock) begin
|
||||
`EXEC_WAIT:begin
|
||||
reg_write_we <= 1;
|
||||
use_exec_reg_addr <= 0;
|
||||
ERROR<=`ERR_NO_ERROR;
|
||||
end
|
||||
`EXEC_DE_LOAD_REG_TO_PARAM:begin
|
||||
PARAM2<=reg_read_port2_data;
|
||||
@ -190,9 +212,7 @@ always @(posedge clock) begin
|
||||
exec_state <= `EXEC_WRITE_ENTRY;
|
||||
PARAM2 <= BIU_DATA;
|
||||
biu_read_request <= 0;
|
||||
biu_data_direction <= 0;
|
||||
end else begin
|
||||
biu_data_direction <= 1;
|
||||
biu_read_request <= 1;
|
||||
end
|
||||
end
|
||||
@ -201,7 +221,7 @@ always @(posedge clock) begin
|
||||
/*necessary for biu to see we went on another state from decode to give us a new instruction*/
|
||||
end
|
||||
`EXEC_WRITE_ENTRY:begin
|
||||
FLAGS[7:0] <= ALU_FLAGS[7:0];
|
||||
EX2DE_FLAGS[7:0] <= ALU_FLAGS[7:0];
|
||||
case(OUT_MOD)
|
||||
3'b000,
|
||||
3'b001,
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
/* processor.v - implementation of most functions of the 9086 processor
|
||||
/* processor.v - Connects the different modules comprising the processor
|
||||
|
||||
This file is part of the 9086 project.
|
||||
|
||||
@ -29,14 +29,17 @@
|
||||
//reset: active low
|
||||
|
||||
module processor (
|
||||
|
||||
/* MISC */ input clock, input reset, output wire HALT,output [`ERROR_BITS-1:0] ERROR
|
||||
/* MEMORY / IO */ ,output [19:0] external_address_bus, inout [15:0] external_data_bus,output read, output write,output BHE,output IOMEM
|
||||
|
||||
`ifdef CALCULATE_IPC
|
||||
/* STATISTICS */ ,output wire new_instruction
|
||||
`endif
|
||||
`ifdef OTUPUT_JSON_STATISTICS
|
||||
/* */ ,output wire [`L1_CACHE_SIZE-1:0] L1_SIZE_STAT, output wire VALID_INSTRUCTION_STAT, output wire jump_req_debug
|
||||
`endif
|
||||
|
||||
);
|
||||
|
||||
|
||||
@ -50,121 +53,140 @@ assign ERROR=(DE_ERROR!=`ERR_NO_ERROR)?DE_ERROR:(EXEC_ERROR!=`ERR_NO_ERROR)?EXEC
|
||||
|
||||
/*############ Execution Unit ################################################### */
|
||||
|
||||
wire [1:0] in_alu_sel1, in_alu_sel2;
|
||||
assign in_alu_sel1 = DE_OUTPUT[44:43];
|
||||
assign in_alu_sel2 = DE_OUTPUT[46:45];
|
||||
|
||||
wire valid_exec_data, set_initial_values;
|
||||
|
||||
wire [`ERROR_BITS-1:0] EXEC_ERROR;
|
||||
|
||||
wire use_exec_reg_addr;
|
||||
|
||||
wire biu_read_request,biu_jump_req,biu_write_request,use_exec_reg_addr;
|
||||
wire [3:0] EXEC_reg_read_port1_addr;
|
||||
wire [15:0] ALU_O;
|
||||
wire [7:0] EX2DE_FLAGS;
|
||||
|
||||
wire [15:0] PARAM1_INIT, PARAM2_INIT;
|
||||
assign PARAM1_INIT = DE_OUTPUT[23:8];
|
||||
assign PARAM2_INIT = DE_OUTPUT[39:24];
|
||||
|
||||
wire [2:0] IN_MOD,OUT_MOD;
|
||||
assign IN_MOD=DE_OUTPUT[2:0];
|
||||
assign OUT_MOD=DE_OUTPUT[49:47];
|
||||
|
||||
wire [`ALU_OP_BITS-1:0] ALU_OP;
|
||||
assign ALU_OP = DE_OUTPUT[42:40];
|
||||
|
||||
wire [15:0] BIU_ADDRESS_INPUT;
|
||||
wire reg_write_we;
|
||||
wire next_exec;
|
||||
|
||||
execute_unit execute_unit (
|
||||
/* GENERAL */ clock, reset, Wbit, valid_exec_data
|
||||
/* */ ,IN_MOD, OUT_MOD,memio_address_select, ProgCount, RM, EXEC_ERROR, write
|
||||
/* */ ,set_initial_values,next_exec
|
||||
/* PARAM */ ,PARAM1_INIT,PARAM2_INIT
|
||||
/***************** GENERAL *****************/
|
||||
/* */ clock, reset, write, EXEC_ERROR
|
||||
|
||||
/*************** INPUT FROM DE ***************/
|
||||
/* SYNC SIGNALS */ ,valid_exec_data,set_initial_values
|
||||
/* INSTR. PARAMS */ ,Wbit, IN_MOD, OUT_MOD, RM
|
||||
/* DATA */ ,PARAM1_INIT,PARAM2_INIT,ProgCount
|
||||
/* STATE CONTROL */ ,next_state
|
||||
/* ALU CONTROL */ ,in_alu_sel1, in_alu_sel2, ALU_OP, ALU_O
|
||||
/* REGISTER DATA */ ,reg_read_port1_data, reg_read_port2_data, EXEC_reg_read_port1_addr, use_exec_reg_addr, reg_write_we
|
||||
/* OTHER */ ,memio_address_select
|
||||
|
||||
/**************** OUTPUT TO DE ****************/
|
||||
/* SYNC SIGNALS */ ,next_exec
|
||||
/* FLAGS */ ,EX2DE_FLAGS
|
||||
/* BIU */ ,BIU_ADDRESS_INPUT, biu_write_request, biu_read_request, BIU_VALID_DATA, BIU_DATA, biu_data_direction, biu_jump_req
|
||||
|
||||
/**************** OUTPUT TO BIU ****************/
|
||||
/* */ ,BIU_ADDRESS_INPUT
|
||||
/* */ ,biu_read_request, biu_jump_req, biu_write_request
|
||||
|
||||
/*************** INPUT FROM BIU ****************/
|
||||
/* */ ,BIU_VALID_DATA, BIU_DATA_DIR
|
||||
|
||||
/************ BIDIRECTIONAL WITH BIU ***********/
|
||||
/* */ ,BIU_DATA
|
||||
|
||||
/***************** REGISTERS *****************/
|
||||
/* */ ,reg_read_port1_data, reg_read_port2_data, EXEC_reg_read_port1_addr
|
||||
/* */ ,use_exec_reg_addr, reg_write_we
|
||||
|
||||
);
|
||||
|
||||
/*############ Bus Interface Unit ############################################### */
|
||||
|
||||
wire [15:0] INSTRUCTION_LOCATION, BIU_ADDRESS_INPUT;
|
||||
wire [15:0] INSTRUCTION_LOCATION;
|
||||
wire [15:0] BIU_DATA;
|
||||
wire [31:0] INSTRUCTION;
|
||||
wire biu_write_request, biu_read_request, BIU_VALID_DATA;
|
||||
wire biu_jump_req, biu_data_direction,VALID_INSTRUCTION;
|
||||
wire VALID_INSTRUCTION_ACK;
|
||||
wire [31:0] IF2DE_INSTRUCTION;
|
||||
wire BIU_VALID_DATA;
|
||||
wire VALID_INSTRUCTION;
|
||||
wire BIU_DATA_DIR;
|
||||
|
||||
BIU BIU(
|
||||
/* Outside world */ clock,reset,external_address_bus
|
||||
/***************** GENERAL *****************/
|
||||
/* */ clock,reset
|
||||
|
||||
/**************** OUTSIDE WORLD ****************/
|
||||
/* */ ,external_address_bus
|
||||
/* */ ,external_data_bus,read,write,BHE,IOMEM
|
||||
/* Internal */ ,INSTRUCTION,VALID_INSTRUCTION,INSTRUCTION_LOCATION,biu_jump_req
|
||||
/* */ ,BIU_ADDRESS_INPUT,BIU_DATA,biu_write_request,biu_read_request,Wbit,BIU_VALID_DATA,MEM_OR_IO
|
||||
/* */ ,VALID_INSTRUCTION_ACK
|
||||
|
||||
/**************** OUTPUT TO DE ****************/
|
||||
/* */ ,IF2DE_INSTRUCTION,VALID_INSTRUCTION,INSTRUCTION_LOCATION
|
||||
/* */ ,BIU_VALID_DATA,BIU_DATA_DIR
|
||||
|
||||
/**************** INPUT FROM DE ****************/
|
||||
,Wbit,MEM_OR_IO,VALID_INSTRUCTION_ACK
|
||||
|
||||
/**************** INPUT FROM EX ****************/
|
||||
/* */ ,biu_jump_req,biu_write_request,biu_read_request
|
||||
/* */ ,BIU_ADDRESS_INPUT
|
||||
|
||||
/************ BIDIRECTIONAL WITH EX ************/
|
||||
/* */ ,BIU_DATA
|
||||
|
||||
`ifdef OTUPUT_JSON_STATISTICS
|
||||
/* Statistics */ ,L1_SIZE_STAT, VALID_INSTRUCTION_STAT
|
||||
/***************** STATISTICS *****************/
|
||||
/* */ ,L1_SIZE_STAT, VALID_INSTRUCTION_STAT
|
||||
`endif
|
||||
|
||||
);
|
||||
|
||||
assign BIU_DATA= biu_data_direction ? 16'hz : (memio_address_select ? reg_read_port1_data : ALU_O);
|
||||
|
||||
/*############ Decoder ########################################################## */
|
||||
|
||||
|
||||
/* verilator lint_off UNUSEDSIGNAL */ //TODO
|
||||
wire [`EXEC_STATE_BITS+`ERROR_BITS+65:0] DE_OUTPUT;
|
||||
wire [`ERROR_BITS-1:0] DE_ERROR;
|
||||
wire valid_exec_data, set_initial_values, Wbit;
|
||||
wire memio_address_select, MEM_OR_IO, VALID_INSTRUCTION_ACK;
|
||||
wire [1:0] in_alu_sel1, in_alu_sel2;
|
||||
wire [2:0] IN_MOD,OUT_MOD, RM;
|
||||
wire [3:0] DE_reg_read_port1_addr,DE_reg_read_port2_addr, reg_write_addr;
|
||||
wire [15:0] PARAM1_INIT, PARAM2_INIT, ProgCount;
|
||||
wire [`ALU_OP_BITS-1:0] ALU_OP;
|
||||
wire [`EXEC_STATE_BITS-1:0] next_state;
|
||||
|
||||
decoder decoder(
|
||||
/* GENERAL */ clock, reset,
|
||||
/* INPUT FROM IF */ INSTRUCTION,VALID_INSTRUCTION,INSTRUCTION_LOCATION
|
||||
/* INPUT FROM EX */ ,EX2DE_FLAGS[7:0],next_exec
|
||||
/* OUTPUT TO EX */ ,DE_OUTPUT
|
||||
/* */ ,ProgCount,set_initial_values,valid_exec_data
|
||||
/* OUTPUT TO IF */ ,VALID_INSTRUCTION_ACK
|
||||
/***************** GENERAL *****************/
|
||||
/* Input from sys. */ clock, reset
|
||||
/* Output to sys. */ ,MEM_OR_IO, DE_ERROR, HALT
|
||||
|
||||
/*************** INPUT FROM IF ***************/
|
||||
/* */ ,IF2DE_INSTRUCTION, VALID_INSTRUCTION
|
||||
/* */ ,INSTRUCTION_LOCATION
|
||||
|
||||
/*************** OUTPUT TO IF ***************/
|
||||
/* */ ,VALID_INSTRUCTION_ACK
|
||||
|
||||
/*************** INPUT FROM EX ***************/
|
||||
/* */ ,EX2DE_FLAGS[7:0], next_exec
|
||||
|
||||
/*************** OUTPUT TO DE ***************/
|
||||
/* SYNC SIGNALS */ ,set_initial_values, valid_exec_data
|
||||
/* INSTR. PARAMS */ ,Wbit, IN_MOD, OUT_MOD, RM
|
||||
/* DATA */ ,PARAM1_INIT, PARAM2_INIT, ProgCount
|
||||
/* STATE CONTROL */ ,next_state
|
||||
/* ALU CONTROL */ ,in_alu_sel1, in_alu_sel2, ALU_OP
|
||||
/* OTHER */ ,memio_address_select
|
||||
|
||||
/************* OUTPUT TO REGISTERS ************/
|
||||
/* */ , reg_write_addr,DE_reg_read_port2_addr, DE_reg_read_port1_addr
|
||||
|
||||
`ifdef CALCULATE_IPC
|
||||
/* STATISTICS */ , new_instruction
|
||||
`endif
|
||||
|
||||
);
|
||||
|
||||
wire [2:0] RM;
|
||||
assign RM = DE_OUTPUT[5:3];
|
||||
|
||||
wire memio_address_select;
|
||||
assign memio_address_select=DE_OUTPUT[6:6];
|
||||
|
||||
wire [3:0] DE_reg_read_port1_addr,DE_reg_read_port2_addr;
|
||||
assign DE_reg_read_port1_addr=DE_OUTPUT[53:50];
|
||||
assign DE_reg_read_port2_addr=DE_OUTPUT[57:54];
|
||||
|
||||
wire [3:0] reg_write_addr;
|
||||
assign reg_write_addr=DE_OUTPUT[61:58];
|
||||
|
||||
wire MEM_OR_IO;
|
||||
assign MEM_OR_IO = DE_OUTPUT[7:7];
|
||||
|
||||
wire Wbit;
|
||||
assign Wbit=DE_OUTPUT[64:64];
|
||||
|
||||
wire [`ERROR_BITS-1:0] DE_ERROR;
|
||||
assign HALT = DE_OUTPUT[65:65];
|
||||
assign DE_ERROR = DE_OUTPUT[`ERROR_BITS+65:66];
|
||||
|
||||
wire [`EXEC_STATE_BITS-1:0] next_state;
|
||||
assign next_state=DE_OUTPUT[`EXEC_STATE_BITS+`ERROR_BITS+65:`ERROR_BITS+66];
|
||||
|
||||
/*############ Registers ######################################################## */
|
||||
|
||||
wire [15:0] ProgCount;
|
||||
|
||||
wire [3:0] reg_read_port1_addr;
|
||||
assign reg_read_port1_addr = use_exec_reg_addr ? EXEC_reg_read_port1_addr : DE_reg_read_port1_addr;
|
||||
|
||||
wire [15:0] reg_read_port1_data, reg_read_port2_data;
|
||||
|
||||
wire reg_write_we;
|
||||
|
||||
register_file register_file(
|
||||
/* WRITE */ .write_port1_addr(reg_write_addr),
|
||||
/* */ .write_port1_data(ALU_O),
|
||||
|
||||
@ -64,6 +64,7 @@ initial begin
|
||||
end else
|
||||
json_file_descriptor=0;
|
||||
`endif
|
||||
sane=0;
|
||||
end
|
||||
|
||||
//integer killswitch=0;
|
||||
@ -132,8 +133,12 @@ always @(posedge clock) begin
|
||||
endcase
|
||||
end
|
||||
|
||||
always @(posedge reset)begin
|
||||
sane<=1;
|
||||
end
|
||||
reg sane;
|
||||
always @( ERROR ) begin
|
||||
if ( ERROR != `ERR_NO_ERROR ) begin
|
||||
if ( ERROR != `ERR_NO_ERROR && sane == 1 ) begin
|
||||
$display("PROCESSOR RUN INTO AN ERROR.");
|
||||
case (ERROR)
|
||||
default:begin
|
||||
|
||||
Loading…
Reference in New Issue
Block a user