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Lots of cleanup mainly on processor.v

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This commit is contained in:
(Tim) Efthimis Kritikos 2023-06-01 02:13:55 +01:00
parent a693b87e96
commit 42c319d55d
6 changed files with 291 additions and 214 deletions
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23
gtkwave_savefile.gtkw
View File

@ -1,15 +1,15 @@
[*] [*]
[*] GTKWave Analyzer v3.3.111 (w)1999-2020 BSI [*] GTKWave Analyzer v3.3.111 (w)1999-2020 BSI
[*] Tue May 16 18:44:13 2023 [*] Wed May 31 20:14:37 2023
[*] [*]
[dumpfile] "/home/user/9086/system/boot_code.fst" [dumpfile] "/home/user/9086/system/boot_code.fst"
[dumpfile_mtime] "Tue May 16 18:40:53 2023" [dumpfile_mtime] "Wed May 31 20:14:23 2023"
[dumpfile_size] 205398 [dumpfile_size] 4718
[savefile] "/home/user/9086/gtkwave_savefile.gtkw" [savefile] "/home/user/9086/gtkwave_savefile.gtkw"
[timestart] 24360000000 [timestart] 500000000
[size] 1140 1003 [size] 1044 1003
[pos] -1 -1 [pos] -1 -1
*-33.095047 38460000000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 *-32.495049 38460000000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[treeopen] TOP. [treeopen] TOP.
[treeopen] TOP.system. [treeopen] TOP.system.
[treeopen] TOP.system.p. [treeopen] TOP.system.p.
@ -33,22 +33,16 @@ TOP.system.p.write
- -
@28 @28
TOP.system.p.BIU.VALID_INSTRUCTION TOP.system.p.BIU.VALID_INSTRUCTION
TOP.system.p.valid_instruction_ack
TOP.system.p.valid_exec_data TOP.system.p.valid_exec_data
@29
TOP.system.p.execute_unit.next_exec TOP.system.p.execute_unit.next_exec
@23
TOP.system.p.IF2DE_INSTRUCTION[31:0]
@22 @22
TOP.system.p.execute_unit.INSTRUCTION_BUFFER[23:0]
TOP.system.p.BIU.biu_state[3:0] TOP.system.p.BIU.biu_state[3:0]
@28 @28
TOP.system.p.execute_unit.exec_state[3:0] TOP.system.p.execute_unit.exec_state[3:0]
TOP.system.p.proc_state[2:0]
TOP.system.p.BIU.write_request TOP.system.p.BIU.write_request
TOP.system.p.BIU.read_request TOP.system.p.BIU.read_request
TOP.system.p.SIMPLE_MICRO
@22
TOP.system.p.ucode_seq_addr[4:0]
@28
TOP.system.p.execute_unit.biu_jump_req TOP.system.p.execute_unit.biu_jump_req
@200 @200
- -
@ -58,7 +52,6 @@ TOP.system.IOMEM
TOP.system.p.HALT TOP.system.p.HALT
@22 @22
TOP.system.p.BIU.INSTRUCTION[31:0] TOP.system.p.BIU.INSTRUCTION[31:0]
TOP.system.p.decoder.seq_addr_entry[4:0]
TOP.system.p.BIU.FIFO_end[3:0] TOP.system.p.BIU.FIFO_end[3:0]
TOP.system.p.BIU.FIFO_start[3:0] TOP.system.p.BIU.FIFO_start[3:0]
TOP.system.p.BIU.INPUT_FIFO[0][7:0] TOP.system.p.BIU.INPUT_FIFO[0][7:0]

41
system/biu.v
View File

@ -38,15 +38,34 @@
`define BIU_GET_SECOND_BYTE1 4'b1110 `define BIU_GET_SECOND_BYTE1 4'b1110
module BIU ( module BIU (
/* Outside world */ input clock, input reset, output reg [19:0] external_address_bus,
/* */ inout [15:0] external_data_bus,output reg read, output reg write,output reg BHE,output reg IOMEM, /***************** GENERAL *****************/
/* Internal */ output reg [31:0] INSTRUCTION, output reg VALID_INSTRUCTION, output reg [15:0] INSTRUCTION_LOCATION, input jump_req, /* */ input clock, input reset
/* */ input[15:0] ADDRESS_INPUT, inout [15:0] DATA, input write_request, input read_request, input Wbit, output reg VALID_DATA, input MEM_OR_IO,
/* */ input valid_instruction_ack /**************** OUTSIDE WORLD ****************/
/* */ ,output reg [19:0] external_address_bus
/* */ ,inout [15:0] external_data_bus,output reg read, output reg write,output reg BHE,output reg IOMEM
/**************** OUTPUT TO DE ****************/
/* */ ,output reg [31:0] INSTRUCTION, output reg VALID_INSTRUCTION, output reg [15:0] INSTRUCTION_LOCATION
/* */ ,output reg VALID_DATA, output reg DATA_DIR
/**************** INPUT FROM DE ****************/
,input Wbit, input MEM_OR_IO, input valid_instruction_ack
/**************** INPUT FROM EX ****************/
/* */ ,input jump_req, input write_request, input read_request
/* */ ,input[15:0] ADDRESS_INPUT
/************ BIDIRECTIONAL WITH EX ************/
/* */ ,inout [15:0] DATA
`ifdef OTUPUT_JSON_STATISTICS `ifdef OTUPUT_JSON_STATISTICS
/* Statistics */ ,output wire [`L1_CACHE_SIZE-1:0] FIFO_SIZE_STAT, output wire VALID_INSTRUCTION_STAT /***************** STATISTICS *****************/
/* */ ,output wire [`L1_CACHE_SIZE-1:0] FIFO_SIZE_STAT, output wire VALID_INSTRUCTION_STAT
`endif `endif
);
);
`ifdef OTUPUT_JSON_STATISTICS `ifdef OTUPUT_JSON_STATISTICS
assign FIFO_SIZE_STAT = FIFO_SIZE; assign FIFO_SIZE_STAT = FIFO_SIZE;
@ -57,7 +76,6 @@ reg [15:0] data_bus_output_register;
assign external_data_bus=read?data_bus_output_register:16'hz; assign external_data_bus=read?data_bus_output_register:16'hz;
reg [15:0] DATA_OUT; reg [15:0] DATA_OUT;
reg DATA_DIR;
assign DATA=DATA_DIR ? 16'hz:DATA_OUT; assign DATA=DATA_DIR ? 16'hz:DATA_OUT;
`define FIFO_SIZE_BYTES $rtoi($pow(2,`L1_CACHE_SIZE)) `define FIFO_SIZE_BYTES $rtoi($pow(2,`L1_CACHE_SIZE))
@ -75,6 +93,10 @@ always @(negedge reset) begin
end end
always @(posedge reset) begin always @(posedge reset) begin
biu_state <= `BIU_RESET; biu_state <= `BIU_RESET;
/* verilator lint_off BLKSEQ */
FIFO_start = `L1_CACHE_SIZE'b0;
/* verilator lint_on BLKSEQ */
FIFO_end <= `L1_CACHE_SIZE'b0;
end end
reg jump_req_latch; reg jump_req_latch;
@ -318,6 +340,7 @@ InstrSize fifoInstrSize2(
always @( valid_instruction_ack ) begin always @( valid_instruction_ack ) begin
/* verilator lint_off BLKSEQ */ /* verilator lint_off BLKSEQ */
FIFO_start = FIFO_start + {{`L1_CACHE_SIZE-3{1'b0}},Isize}; FIFO_start = FIFO_start + {{`L1_CACHE_SIZE-3{1'b0}},Isize};
/* verilator lint_on BLKSEQ */
INSTRUCTION_LOCATION <= INSTRUCTION_LOCATION + {13'd0,Isize}; INSTRUCTION_LOCATION <= INSTRUCTION_LOCATION + {13'd0,Isize};
`ifdef DOUBLE_INSTRUCTION_LOAD `ifdef DOUBLE_INSTRUCTION_LOAD
if(FIFO_SIZE>`L1_CACHE_SIZE'd3+{{`L1_CACHE_SIZE-3{1'b0}},Isize})begin if(FIFO_SIZE>`L1_CACHE_SIZE'd3+{{`L1_CACHE_SIZE-3{1'b0}},Isize})begin
@ -340,7 +363,6 @@ always @( valid_instruction_ack ) begin
VALID_INSTRUCTION <= 0; VALID_INSTRUCTION <= 0;
end else begin end else begin
VALID_INSTRUCTION <= 0; VALID_INSTRUCTION <= 0;
/* verilator lint_on BLKSEQ */
end end
`else `else
VALID_INSTRUCTION <= 0; VALID_INSTRUCTION <= 0;
@ -349,6 +371,7 @@ end
always @( posedge jump_req ) begin always @( posedge jump_req ) begin
jump_req_latch <= 1; jump_req_latch <= 1;
DATA_DIR <= 1;
VALID_INSTRUCTION <= 0; VALID_INSTRUCTION <= 0;
end end

182
system/decoder.v
View File

@ -24,34 +24,70 @@
`include "config.v" `include "config.v"
`define DE_STATE_BITS 2 `define DE_STATE_BITS 2
`define DE_RESET 2'b00
`define DE_STATE_ENTRY 2'b01 `define DE_STATE_ENTRY 2'b01
`define DE_HALT 2'b10 `define DE_HALT 2'b10
module decoder( module decoder(
/* GENERAL */ input clock, input reset /***************** GENERAL *****************/
/* INPUT FROM IF */ ,input wire [31:0] IF2DE_INSTRUCTION,input wire VALID_INSTRUCTION, input [15:0] INSTRUCTION_LOCATION /* Input from sys. */ input clock, input reset
/* INPUT FROM EX */ ,input wire [7:0] EX2DE_FLAGS,input wire next_exec /* Output to sys. */ ,output reg MEM_OR_IO_LATCHED, output reg [`ERROR_BITS-1:0] ERROR_LATCHED, output reg HALT_LATCHED
/* OUTPUT TO EX */ ,output reg [`EXEC_STATE_BITS+`ERROR_BITS+65:0] DE_OUTPUT_sampled
/* */ ,output reg [15:0] ProgCount, output reg set_initial_values,output reg valid_exec_data /*************** INPUT FROM IF ***************/
/* */ ,input wire [31:0] IF2DE_INSTRUCTION, input wire VALID_INSTRUCTION
/* */ ,input wire [15:0] INSTRUCTION_LOCATION
/*************** OUTPUT TO IF ***************/
/* OUTPUT TO IF */ ,output reg VALID_INSTRUCTION_ACK /* OUTPUT TO IF */ ,output reg VALID_INSTRUCTION_ACK
/*************** INPUT FROM EX ***************/
/* */ ,input wire [7:0] EX2DE_FLAGS,input wire next_exec
/*************** OUTPUT TO DE ***************/
/* SYNC SIGNALS */ ,output reg set_initial_values, output reg valid_exec_data
/* INSTR. PARAMS */ ,output reg Wbit_LATCHED, output reg [2:0] IN_MOD_LATCHED, output reg [2:0] OUT_MOD_LATCHED, output reg [2:0] RM_LATCHED
/* DATA */ ,output reg [15:0] PARAM1_LATCHED, output reg [15:0] PARAM2_LATCHED,output reg [15:0] ProgCount
/* STATE CONTROL */ ,output reg [`EXEC_STATE_BITS-1:0] next_state_LATCHED
/* ALU CONTROL */ ,output reg [1:0] in_alu_sel1_LATCHED, output reg [1:0] in_alu_sel2_LATCHED,output reg [2:0] ALU_OP_LATCHED
/* OTHER */ ,output reg memio_address_select_LATCHED
/************* OUTPUT TO REGISTERS ************/
/* */ ,output reg [3:0] reg_write_addr_LATCHED, output reg [3:0] reg_read_port2_addr_LATCHED, output reg [3:0] reg_read_port1_addr_LATCHED
`ifdef CALCULATE_IPC `ifdef CALCULATE_IPC
/* STATISTICS */ ,output reg new_instruction /* STATISTICS */ ,output reg new_instruction
`endif `endif
); );
reg SIMPLE_MICRO; /* use simple decodings (=0) or microcode data (=1) */ reg SIMPLE_MICRO; /* use simple decodings (=0) or microcode data (=1) */
wire [`UCODE_ADDR_BITS-1:0] ucode_seq_addr_entry; wire [`UCODE_ADDR_BITS-1:0] ucode_seq_addr_entry;
reg [`UCODE_ADDR_BITS-1:0] ucode_seq_addr; reg [`UCODE_ADDR_BITS-1:0] ucode_seq_addr;
wire DEPENDS_ON_PREVIOUS; wire DEPENDS_ON_PREVIOUS;
wire [`EXEC_STATE_BITS+`ERROR_BITS+65:0] DE_OUTPUT;
wire set_params; wire set_params;
wire MEM_OR_IO, HALT,Wbit,memio_address_select;
wire [1:0] in_alu_sel1,in_alu_sel2;
wire [2:0] IN_MOD,OUT_MOD,RM,ALU_OP;
wire [3:0] reg_write_addr,reg_read_port2_addr,reg_read_port1_addr;
wire [15:0] PARAM1,PARAM2;
wire [`EXEC_STATE_BITS-1:0] next_state;
wire [`ERROR_BITS-1:0] ERROR;
instruction_decode instruction_decode( instruction_decode instruction_decode(
/* INPUT */ IF2DE_INSTRUCTION,{8'h0,EX2DE_FLAGS}, /* INPUT */ IF2DE_INSTRUCTION,{8'h0,EX2DE_FLAGS}
/* MICROCODE */ ucode_seq_addr_entry,SIMPLE_MICRO,ucode_seq_addr, /* MICROCODE */ ,ucode_seq_addr_entry,SIMPLE_MICRO,ucode_seq_addr
/* OUTPUT */ DE_OUTPUT,DEPENDS_ON_PREVIOUS, set_params /* OUTPUT */ ,DEPENDS_ON_PREVIOUS, set_params, MEM_OR_IO,ERROR, HALT
);
/*************** INPUT FROM DE ***************/
/* INSTR. PARAMS */ ,Wbit, IN_MOD, OUT_MOD, RM
/* DATA */ ,PARAM1, PARAM2
/* STATE CONTROL */ ,next_state
/* ALU CONTROL */ ,in_alu_sel1,in_alu_sel2, ALU_OP
/* OTHER */ ,memio_address_select
/***************** REGISTERS *****************/
/* */ ,reg_write_addr, reg_read_port2_addr, reg_read_port1_addr
);
reg [`DE_STATE_BITS-1:0] de_state; reg [`DE_STATE_BITS-1:0] de_state;
@ -61,15 +97,25 @@ always @(negedge reset) begin
`ifdef CALCULATE_IPC `ifdef CALCULATE_IPC
new_instruction<=0; new_instruction<=0;
`endif `endif
end valid_exec_data<=0;
always @(posedge reset) begin
de_state <= `DE_RESET;
/* need early init */
VALID_INSTRUCTION_ACK <= 0;
instant_response <= 0; instant_response <= 0;
stalled_response <= 0; stalled_response <= 0;
end end
always @(posedge reset) begin
de_state <= `DE_STATE_ENTRY;
/* need early init */
ucode_seq_addr <= `UCODE_NO_INSTRUCTION;
SIMPLE_MICRO <= 0;
owe_set_init <= 0;
set_initial_values<=0;
wait_exec<=0;
first_ucode <= 0;
HALT_LATCHED <= 0;
ERROR_LATCHED <= `ERROR_BITS'h0;
VALID_INSTRUCTION_ACK <= 0;
end
wire [2:0] instr_end; wire [2:0] instr_end;
InstrSize InstrSize({IF2DE_INSTRUCTION[31:24],IF2DE_INSTRUCTION[21:19]},instr_end); InstrSize InstrSize({IF2DE_INSTRUCTION[31:24],IF2DE_INSTRUCTION[21:19]},instr_end);
@ -96,8 +142,24 @@ end
reg first_ucode; reg first_ucode;
always @(instant_response or stalled_response) begin always @(instant_response or stalled_response) begin
DE_OUTPUT_sampled <= DE_OUTPUT; //`define LATCH(VAR) VAR_LATCHED <= VAR; //TODO would this work?
IN_MOD_LATCHED <= IN_MOD;
OUT_MOD_LATCHED <= OUT_MOD;
RM_LATCHED <= RM;
MEM_OR_IO_LATCHED <= MEM_OR_IO;
PARAM1_LATCHED <= PARAM1;
PARAM2_LATCHED <= PARAM2;
ALU_OP_LATCHED <= ALU_OP;
in_alu_sel1_LATCHED <= in_alu_sel1;
in_alu_sel2_LATCHED <= in_alu_sel2;
reg_read_port1_addr_LATCHED <= reg_read_port1_addr;
reg_read_port2_addr_LATCHED <= reg_read_port2_addr;
reg_write_addr_LATCHED <= reg_write_addr;
Wbit_LATCHED <= Wbit;
ERROR_LATCHED <= ERROR;
HALT_LATCHED <= HALT;
next_state_LATCHED <= next_state;
memio_address_select_LATCHED <= memio_address_select;
if ( (ucode_seq_addr==`UCODE_NO_INSTRUCTION) && (ucode_seq_addr_entry!=`UCODE_NO_INSTRUCTION) )begin if ( (ucode_seq_addr==`UCODE_NO_INSTRUCTION) && (ucode_seq_addr_entry!=`UCODE_NO_INSTRUCTION) )begin
/* switch to microcode decoding */ /* switch to microcode decoding */
@ -138,17 +200,6 @@ end
always @(posedge clock) begin always @(posedge clock) begin
case(de_state) case(de_state)
`DE_RESET:begin
ucode_seq_addr <= `UCODE_NO_INSTRUCTION;
DE_OUTPUT_sampled <= 0;
SIMPLE_MICRO <= 0;
de_state <= `DE_STATE_ENTRY;
owe_set_init <= 0;
set_initial_values<=0;
wait_exec<=0;
valid_exec_data<=0;
first_ucode <= 0;
end
`DE_STATE_ENTRY:begin `DE_STATE_ENTRY:begin
if ( ( VALID_INSTRUCTION==1 || SIMPLE_MICRO == 1 ) && wait_exec==0) begin if ( ( VALID_INSTRUCTION==1 || SIMPLE_MICRO == 1 ) && wait_exec==0) begin
stalled_response <= !stalled_response; stalled_response <= !stalled_response;
@ -164,12 +215,12 @@ end
endmodule endmodule
/************************ Instruction specific decoding **********************************/ ///////////////////////// Instruction specific decoding ///////////////////////////////////
module microcode( module microcode(
input [`UCODE_ADDR_BITS-1:0] ADDR, input [`UCODE_ADDR_BITS-1:0] ADDR
output [`UCODE_DATA_BITS-1:0] DATA ,output [`UCODE_DATA_BITS-1:0] DATA
); );
initial begin initial begin
@ -191,62 +242,23 @@ endmodule
module instruction_decode( module instruction_decode(
/* INPUTS */ input wire [31:0] INSTRUCTION,input wire [15:0] FLAGS /* INPUTS */ input wire [31:0] INSTRUCTION,input wire [15:0] FLAGS
/* MICROCODE */ ,output reg [`UCODE_ADDR_BITS-1:0] seq_addr_entry, input wire SIMPLE_MICRO, input wire [`UCODE_ADDR_BITS-1:0] seq_addr_input /* MICROCODE */ ,output reg [`UCODE_ADDR_BITS-1:0] seq_addr_entry, input wire SIMPLE_MICRO, input wire [`UCODE_ADDR_BITS-1:0] seq_addr_input
/* OUTPUT */ ,output wire [`EXEC_STATE_BITS+`ERROR_BITS+65:0] OUTPUT, output reg DEPENDS_ON_PREVIOUS, output reg set_params /* OUTPUT */ ,output reg DEPENDS_ON_PREVIOUS, output reg set_params,output reg MEM_OR_IO, output reg [`ERROR_BITS-1:0] ERROR, output reg HALT
/*************** INPUT FROM DE ***************/
/* INSTR. PARAMS */ ,output reg Wbit, output reg [2:0] IN_MOD, output reg [2:0] OUT_MOD, output reg [2:0] RM
/* DATA */ ,output reg [15:0] PARAM1, output reg [15:0] PARAM2
/* STATE CONTROL */ ,output reg [`EXEC_STATE_BITS-1:0] next_state
/* ALU CONTROL */ ,output reg [1:0] in_alu_sel1, output reg [1:0] in_alu_sel2,output reg [2:0] ALU_OP
/* OTHER */ ,output reg memio_address_select
/***************** REGISTERS *****************/
/* */ ,output reg [3:0] reg_write_addr, output reg [3:0] reg_read_port2_addr, output reg [3:0] reg_read_port1_addr
); );
/* DEPENDS_ON_PREVIOUS - This encodes weather the instruction requires the previous to be finished in order to be decoded. This, for example, affects /* DEPENDS_ON_PREVIOUS - This encodes weather the instruction requires the previous to be finished in order to be decoded. This, for example, affects
* conditional jumps since flags are checked during decode. * conditional jumps since flags are checked during decode.
*/ */
reg [2:0]IN_MOD;
assign OUTPUT[2:0] = IN_MOD;
reg [2:0]RM;
assign OUTPUT[5:3] = RM;
reg memio_address_select;
assign OUTPUT[6:6] = memio_address_select;
reg MEM_OR_IO;
assign OUTPUT[7:7] = MEM_OR_IO;
reg [15:0] PARAM1;
assign OUTPUT[23:8] = PARAM1;
reg [15:0] PARAM2;
assign OUTPUT[39:24] = PARAM2;
reg [2:0]ALU_OP;
assign OUTPUT[42:40] = ALU_OP;
reg [1:0]in_alu_sel1;
assign OUTPUT[44:43] = in_alu_sel1;
reg [1:0]in_alu_sel2;
assign OUTPUT[46:45] = in_alu_sel2;
reg [2:0]OUT_MOD;
assign OUTPUT[49:47] = OUT_MOD;
reg [3:0]reg_read_port1_addr;
assign OUTPUT[53:50] = reg_read_port1_addr;
reg [3:0]reg_read_port2_addr;
assign OUTPUT[57:54] = reg_read_port2_addr;
reg [3:0]reg_write_addr;
assign OUTPUT[61:58] = reg_write_addr;
reg Wbit,Sbit,opcode_size;
assign OUTPUT[64:62] = {Wbit,Sbit,opcode_size};
reg [`ERROR_BITS-1:0] ERROR;
reg HALT;
assign OUTPUT[`ERROR_BITS+65:65]={ERROR,HALT};
reg [`EXEC_STATE_BITS-1:0] next_state;
assign OUTPUT[`EXEC_STATE_BITS+`ERROR_BITS+65:`ERROR_BITS+66] = next_state;
/* verilator lint_off UNUSEDSIGNAL */ /* verilator lint_off UNUSEDSIGNAL */
wire [`UCODE_DATA_BITS-1:0] ucode_data; wire [`UCODE_DATA_BITS-1:0] ucode_data;
/* verilator lint_on UNUSEDSIGNAL */ /* verilator lint_on UNUSEDSIGNAL */
@ -269,10 +281,12 @@ reg [1:0] PARAM_ACTION;
`define LOAD_8 2'b01 `define LOAD_8 2'b01
`define LOAD_16 2'b10 `define LOAD_16 2'b10
reg Sbit,opcode_size;
// I use blocking for basically putting names on the different fields of INSTRUCTION and // I use blocking for basically putting names on the different fields of INSTRUCTION and
// then branching off of that instead of the raw bits. otherwise the code // then branching off of that instead of the raw bits. otherwise the code
// would be identical // would be identical
// verilator lint_off BLKSEQ /* verilator lint_off BLKSEQ */
always @( FLAGS or INSTRUCTION or SIMPLE_MICRO or seq_addr_input ) begin always @( FLAGS or INSTRUCTION or SIMPLE_MICRO or seq_addr_input ) begin
set_params = 1; set_params = 1;
PARAM_ACTION = `NO_LOAD; PARAM_ACTION = `NO_LOAD;
@ -1009,7 +1023,7 @@ end
`undef invalid_instruction `undef invalid_instruction
endmodule endmodule
// verilator lint_on BLKSEQ /* verilator lint_on BLKSEQ */
/* IN: {INSTRUCTION[31:24],INSTRUCTION[21:19]} */ /* IN: {INSTRUCTION[31:24],INSTRUCTION[21:19]} */

44
system/execute.v
View File

@ -22,22 +22,43 @@
`include "error_header.v" `include "error_header.v"
module execute_unit ( module execute_unit (
/* GENERAL */ input clock, input reset ,input Wbit , input valid_input /***************** GENERAL *****************/
/* */ ,input [2:0] IN_MOD, input [2:0] OUT_MOD, input memio_address_select, input [15:0] ProgCount, input [2:0] RM, output reg [`ERROR_BITS-1:0] ERROR , input write /*TODO: REMOVE!!*/ /* */ input clock, input reset, input write /*TODO: REMOVE!!*/, output reg [`ERROR_BITS-1:0] ERROR
/* */ ,input set_initial_values, output reg next_exec
/* PARAM */ ,input [15:0] PARAM1_INIT, input [15:0] PARAM2_INIT /*************** INPUT FROM DE ***************/
/* SYNC SIGNALS */ ,input valid_input,input set_initial_values
/* INSTR. PARAMS */ ,input Wbit ,input [2:0] IN_MOD, input [2:0] OUT_MOD, input [2:0] RM
/* DATA */ ,input [15:0] PARAM1_INIT, input [15:0] PARAM2_INIT, input [15:0] ProgCount
/* STATE CONTROL */ ,input [`EXEC_STATE_BITS-1:0] init_state /* STATE CONTROL */ ,input [`EXEC_STATE_BITS-1:0] init_state
/* ALU CONTROL */ ,input [1:0] in_alu_sel1, input [1:0] in_alu_sel2, input [`ALU_OP_BITS-1:0] ALU_OP, output [15:0] _ALU_O_ /* ALU CONTROL */ ,input [1:0] in_alu_sel1, input [1:0] in_alu_sel2, input [`ALU_OP_BITS-1:0] ALU_OP, output [15:0] _ALU_O_
/* REGISTER DATA */ ,input [15:0] reg_read_port1_data ,input [15:0] reg_read_port2_data, output reg [3:0] reg_read_port1_addr, output reg use_exec_reg_addr, output reg reg_write_we /* OTHER */ ,input memio_address_select
/* FLAGS */ ,output reg [7:0] FLAGS
/* BIU */ ,output reg [15:0] BIU_ADDRESS_INPUT,output reg biu_write_request, output reg biu_read_request, input BIU_VALID_DATA, input [15:0] BIU_DATA, output reg biu_data_direction, output reg biu_jump_req /**************** OUTPUT TO DE ****************/
); /* SYNC SIGNALS */ ,output reg next_exec
/* FLAGS */ ,output reg [7:0] EX2DE_FLAGS
/**************** OUTPUT TO BIU ****************/
/* */ ,output reg [15:0] BIU_ADDRESS_INPUT
/* */ ,output reg biu_read_request, output reg biu_jump_req,output reg biu_write_request
/*************** INPUT FROM BIU ****************/
/* */ ,input BIU_VALID_DATA, input biu_data_direction
/************ BIDIRECTIONAL WITH BIU ***********/
/* */ ,inout [15:0] BIU_DATA
/***************** REGISTERS *****************/
/* */ ,input [15:0] reg_read_port1_data ,input [15:0] reg_read_port2_data, output reg [3:0] reg_read_port1_addr
/* */ ,output reg use_exec_reg_addr, output reg reg_write_we
);
assign _ALU_O_ = ALU_O; assign _ALU_O_ = ALU_O;
reg [`EXEC_STATE_BITS-1:0] exec_state; reg [`EXEC_STATE_BITS-1:0] exec_state;
reg [15:0] PARAM1,PARAM2; reg [15:0] PARAM1,PARAM2;
assign BIU_DATA = biu_data_direction ? (memio_address_select ? reg_read_port1_data : ALU_O): 16'hz;
/*############ ALU / Execution units ################################################## */ /*############ ALU / Execution units ################################################## */
mux4 #(.WIDTH(16)) MUX16_1A( mux4 #(.WIDTH(16)) MUX16_1A(
@ -90,6 +111,7 @@ end
always @(posedge reset) begin always @(posedge reset) begin
exec_state <= `EXEC_RESET; exec_state <= `EXEC_RESET;
next_exec <= 0;
end end
`define unimpl_addressing_mode exec_state <= `EXEC_WAIT;ERROR <= `ERR_UNIMPL_ADDRESSING_MODE; `define unimpl_addressing_mode exec_state <= `EXEC_WAIT;ERROR <= `ERR_UNIMPL_ADDRESSING_MODE;
@ -101,7 +123,6 @@ always @(posedge clock) begin
`EXEC_RESET: begin `EXEC_RESET: begin
biu_write_request <= 0; biu_write_request <= 0;
biu_read_request <= 0; biu_read_request <= 0;
biu_data_direction <= 0;
biu_jump_req <= 0; biu_jump_req <= 0;
reg_write_we <= 1; reg_write_we <= 1;
exec_state <= `EXEC_WAIT; exec_state <= `EXEC_WAIT;
@ -111,6 +132,7 @@ always @(posedge clock) begin
`EXEC_WAIT:begin `EXEC_WAIT:begin
reg_write_we <= 1; reg_write_we <= 1;
use_exec_reg_addr <= 0; use_exec_reg_addr <= 0;
ERROR<=`ERR_NO_ERROR;
end end
`EXEC_DE_LOAD_REG_TO_PARAM:begin `EXEC_DE_LOAD_REG_TO_PARAM:begin
PARAM2<=reg_read_port2_data; PARAM2<=reg_read_port2_data;
@ -190,9 +212,7 @@ always @(posedge clock) begin
exec_state <= `EXEC_WRITE_ENTRY; exec_state <= `EXEC_WRITE_ENTRY;
PARAM2 <= BIU_DATA; PARAM2 <= BIU_DATA;
biu_read_request <= 0; biu_read_request <= 0;
biu_data_direction <= 0;
end else begin end else begin
biu_data_direction <= 1;
biu_read_request <= 1; biu_read_request <= 1;
end end
end end
@ -201,7 +221,7 @@ always @(posedge clock) begin
/*necessary for biu to see we went on another state from decode to give us a new instruction*/ /*necessary for biu to see we went on another state from decode to give us a new instruction*/
end end
`EXEC_WRITE_ENTRY:begin `EXEC_WRITE_ENTRY:begin
FLAGS[7:0] <= ALU_FLAGS[7:0]; EX2DE_FLAGS[7:0] <= ALU_FLAGS[7:0];
case(OUT_MOD) case(OUT_MOD)
3'b000, 3'b000,
3'b001, 3'b001,

186
system/processor.v
View File

@ -1,4 +1,4 @@
/* processor.v - implementation of most functions of the 9086 processor /* processor.v - Connects the different modules comprising the processor
This file is part of the 9086 project. This file is part of the 9086 project.
@ -29,15 +29,18 @@
//reset: active low //reset: active low
module processor ( module processor (
/* MISC */ input clock, input reset, output wire HALT,output [`ERROR_BITS-1:0] ERROR /* MISC */ input clock, input reset, output wire HALT,output [`ERROR_BITS-1:0] ERROR
/* MEMORY / IO */ ,output [19:0] external_address_bus, inout [15:0] external_data_bus,output read, output write,output BHE,output IOMEM /* MEMORY / IO */ ,output [19:0] external_address_bus, inout [15:0] external_data_bus,output read, output write,output BHE,output IOMEM
`ifdef CALCULATE_IPC `ifdef CALCULATE_IPC
/* STATISTICS */ ,output wire new_instruction /* STATISTICS */ ,output wire new_instruction
`endif `endif
`ifdef OTUPUT_JSON_STATISTICS `ifdef OTUPUT_JSON_STATISTICS
/* */ ,output wire [`L1_CACHE_SIZE-1:0] L1_SIZE_STAT, output wire VALID_INSTRUCTION_STAT, output wire jump_req_debug /* */ ,output wire [`L1_CACHE_SIZE-1:0] L1_SIZE_STAT, output wire VALID_INSTRUCTION_STAT, output wire jump_req_debug
`endif `endif
);
);
`ifdef OTUPUT_JSON_STATISTICS `ifdef OTUPUT_JSON_STATISTICS
@ -50,121 +53,140 @@ assign ERROR=(DE_ERROR!=`ERR_NO_ERROR)?DE_ERROR:(EXEC_ERROR!=`ERR_NO_ERROR)?EXEC
/*############ Execution Unit ################################################### */ /*############ Execution Unit ################################################### */
wire [1:0] in_alu_sel1, in_alu_sel2;
assign in_alu_sel1 = DE_OUTPUT[44:43];
assign in_alu_sel2 = DE_OUTPUT[46:45];
wire valid_exec_data, set_initial_values;
wire [`ERROR_BITS-1:0] EXEC_ERROR; wire [`ERROR_BITS-1:0] EXEC_ERROR;
wire use_exec_reg_addr; wire biu_read_request,biu_jump_req,biu_write_request,use_exec_reg_addr;
wire [3:0] EXEC_reg_read_port1_addr; wire [3:0] EXEC_reg_read_port1_addr;
wire [15:0] ALU_O; wire [15:0] ALU_O;
wire [7:0]EX2DE_FLAGS; wire [7:0] EX2DE_FLAGS;
wire [15:0] BIU_ADDRESS_INPUT;
wire [15:0] PARAM1_INIT, PARAM2_INIT; wire reg_write_we;
assign PARAM1_INIT = DE_OUTPUT[23:8];
assign PARAM2_INIT = DE_OUTPUT[39:24];
wire [2:0] IN_MOD,OUT_MOD;
assign IN_MOD=DE_OUTPUT[2:0];
assign OUT_MOD=DE_OUTPUT[49:47];
wire [`ALU_OP_BITS-1:0] ALU_OP;
assign ALU_OP = DE_OUTPUT[42:40];
wire next_exec; wire next_exec;
execute_unit execute_unit ( execute_unit execute_unit (
/* GENERAL */ clock, reset, Wbit, valid_exec_data /***************** GENERAL *****************/
/* */ ,IN_MOD, OUT_MOD,memio_address_select, ProgCount, RM, EXEC_ERROR, write /* */ clock, reset, write, EXEC_ERROR
/* */ ,set_initial_values,next_exec
/* PARAM */ ,PARAM1_INIT,PARAM2_INIT /*************** INPUT FROM DE ***************/
/* SYNC SIGNALS */ ,valid_exec_data,set_initial_values
/* INSTR. PARAMS */ ,Wbit, IN_MOD, OUT_MOD, RM
/* DATA */ ,PARAM1_INIT,PARAM2_INIT,ProgCount
/* STATE CONTROL */ ,next_state /* STATE CONTROL */ ,next_state
/* ALU CONTROL */ ,in_alu_sel1, in_alu_sel2, ALU_OP, ALU_O /* ALU CONTROL */ ,in_alu_sel1, in_alu_sel2, ALU_OP, ALU_O
/* REGISTER DATA */ ,reg_read_port1_data, reg_read_port2_data, EXEC_reg_read_port1_addr, use_exec_reg_addr, reg_write_we /* OTHER */ ,memio_address_select
/**************** OUTPUT TO DE ****************/
/* SYNC SIGNALS */ ,next_exec
/* FLAGS */ ,EX2DE_FLAGS /* FLAGS */ ,EX2DE_FLAGS
/* BIU */ ,BIU_ADDRESS_INPUT, biu_write_request, biu_read_request, BIU_VALID_DATA, BIU_DATA, biu_data_direction, biu_jump_req
); /**************** OUTPUT TO BIU ****************/
/* */ ,BIU_ADDRESS_INPUT
/* */ ,biu_read_request, biu_jump_req, biu_write_request
/*************** INPUT FROM BIU ****************/
/* */ ,BIU_VALID_DATA, BIU_DATA_DIR
/************ BIDIRECTIONAL WITH BIU ***********/
/* */ ,BIU_DATA
/***************** REGISTERS *****************/
/* */ ,reg_read_port1_data, reg_read_port2_data, EXEC_reg_read_port1_addr
/* */ ,use_exec_reg_addr, reg_write_we
);
/*############ Bus Interface Unit ############################################### */ /*############ Bus Interface Unit ############################################### */
wire [15:0] INSTRUCTION_LOCATION, BIU_ADDRESS_INPUT; wire [15:0] INSTRUCTION_LOCATION;
wire [15:0] BIU_DATA; wire [15:0] BIU_DATA;
wire [31:0] INSTRUCTION; wire [31:0] IF2DE_INSTRUCTION;
wire biu_write_request, biu_read_request, BIU_VALID_DATA; wire BIU_VALID_DATA;
wire biu_jump_req, biu_data_direction,VALID_INSTRUCTION; wire VALID_INSTRUCTION;
wire VALID_INSTRUCTION_ACK; wire BIU_DATA_DIR;
BIU BIU( BIU BIU(
/* Outside world */ clock,reset,external_address_bus /***************** GENERAL *****************/
/* */ ,external_data_bus,read,write,BHE,IOMEM /* */ clock,reset
/* Internal */ ,INSTRUCTION,VALID_INSTRUCTION,INSTRUCTION_LOCATION,biu_jump_req
/* */ ,BIU_ADDRESS_INPUT,BIU_DATA,biu_write_request,biu_read_request,Wbit,BIU_VALID_DATA,MEM_OR_IO /**************** OUTSIDE WORLD ****************/
/* */ ,VALID_INSTRUCTION_ACK /* */ ,external_address_bus
`ifdef OTUPUT_JSON_STATISTICS /* */ ,external_data_bus,read,write,BHE,IOMEM
/* Statistics */ ,L1_SIZE_STAT, VALID_INSTRUCTION_STAT
`endif /**************** OUTPUT TO DE ****************/
); /* */ ,IF2DE_INSTRUCTION,VALID_INSTRUCTION,INSTRUCTION_LOCATION
/* */ ,BIU_VALID_DATA,BIU_DATA_DIR
/**************** INPUT FROM DE ****************/
,Wbit,MEM_OR_IO,VALID_INSTRUCTION_ACK
/**************** INPUT FROM EX ****************/
/* */ ,biu_jump_req,biu_write_request,biu_read_request
/* */ ,BIU_ADDRESS_INPUT
/************ BIDIRECTIONAL WITH EX ************/
/* */ ,BIU_DATA
`ifdef OTUPUT_JSON_STATISTICS
/***************** STATISTICS *****************/
/* */ ,L1_SIZE_STAT, VALID_INSTRUCTION_STAT
`endif
);
assign BIU_DATA= biu_data_direction ? 16'hz : (memio_address_select ? reg_read_port1_data : ALU_O);
/*############ Decoder ########################################################## */ /*############ Decoder ########################################################## */
/* verilator lint_off UNUSEDSIGNAL */ //TODO wire [`ERROR_BITS-1:0] DE_ERROR;
wire [`EXEC_STATE_BITS+`ERROR_BITS+65:0] DE_OUTPUT; wire valid_exec_data, set_initial_values, Wbit;
wire memio_address_select, MEM_OR_IO, VALID_INSTRUCTION_ACK;
wire [1:0] in_alu_sel1, in_alu_sel2;
wire [2:0] IN_MOD,OUT_MOD, RM;
wire [3:0] DE_reg_read_port1_addr,DE_reg_read_port2_addr, reg_write_addr;
wire [15:0] PARAM1_INIT, PARAM2_INIT, ProgCount;
wire [`ALU_OP_BITS-1:0] ALU_OP;
wire [`EXEC_STATE_BITS-1:0] next_state;
decoder decoder( decoder decoder(
/* GENERAL */ clock, reset, /***************** GENERAL *****************/
/* INPUT FROM IF */ INSTRUCTION,VALID_INSTRUCTION,INSTRUCTION_LOCATION /* Input from sys. */ clock, reset
/* INPUT FROM EX */ ,EX2DE_FLAGS[7:0],next_exec /* Output to sys. */ ,MEM_OR_IO, DE_ERROR, HALT
/* OUTPUT TO EX */ ,DE_OUTPUT
/* */ ,ProgCount,set_initial_values,valid_exec_data /*************** INPUT FROM IF ***************/
/* OUTPUT TO IF */ ,VALID_INSTRUCTION_ACK /* */ ,IF2DE_INSTRUCTION, VALID_INSTRUCTION
/* */ ,INSTRUCTION_LOCATION
/*************** OUTPUT TO IF ***************/
/* */ ,VALID_INSTRUCTION_ACK
/*************** INPUT FROM EX ***************/
/* */ ,EX2DE_FLAGS[7:0], next_exec
/*************** OUTPUT TO DE ***************/
/* SYNC SIGNALS */ ,set_initial_values, valid_exec_data
/* INSTR. PARAMS */ ,Wbit, IN_MOD, OUT_MOD, RM
/* DATA */ ,PARAM1_INIT, PARAM2_INIT, ProgCount
/* STATE CONTROL */ ,next_state
/* ALU CONTROL */ ,in_alu_sel1, in_alu_sel2, ALU_OP
/* OTHER */ ,memio_address_select
/************* OUTPUT TO REGISTERS ************/
/* */ , reg_write_addr,DE_reg_read_port2_addr, DE_reg_read_port1_addr
`ifdef CALCULATE_IPC `ifdef CALCULATE_IPC
/* STATISTICS */ , new_instruction /* STATISTICS */ , new_instruction
`endif `endif
);
wire [2:0] RM; );
assign RM = DE_OUTPUT[5:3];
wire memio_address_select;
assign memio_address_select=DE_OUTPUT[6:6];
wire [3:0] DE_reg_read_port1_addr,DE_reg_read_port2_addr;
assign DE_reg_read_port1_addr=DE_OUTPUT[53:50];
assign DE_reg_read_port2_addr=DE_OUTPUT[57:54];
wire [3:0] reg_write_addr;
assign reg_write_addr=DE_OUTPUT[61:58];
wire MEM_OR_IO;
assign MEM_OR_IO = DE_OUTPUT[7:7];
wire Wbit;
assign Wbit=DE_OUTPUT[64:64];
wire [`ERROR_BITS-1:0] DE_ERROR;
assign HALT = DE_OUTPUT[65:65];
assign DE_ERROR = DE_OUTPUT[`ERROR_BITS+65:66];
wire [`EXEC_STATE_BITS-1:0] next_state;
assign next_state=DE_OUTPUT[`EXEC_STATE_BITS+`ERROR_BITS+65:`ERROR_BITS+66];
/*############ Registers ######################################################## */ /*############ Registers ######################################################## */
wire [15:0] ProgCount;
wire [3:0] reg_read_port1_addr; wire [3:0] reg_read_port1_addr;
assign reg_read_port1_addr = use_exec_reg_addr ? EXEC_reg_read_port1_addr : DE_reg_read_port1_addr; assign reg_read_port1_addr = use_exec_reg_addr ? EXEC_reg_read_port1_addr : DE_reg_read_port1_addr;
wire [15:0] reg_read_port1_data, reg_read_port2_data; wire [15:0] reg_read_port1_data, reg_read_port2_data;
wire reg_write_we;
register_file register_file( register_file register_file(
/* WRITE */ .write_port1_addr(reg_write_addr), /* WRITE */ .write_port1_addr(reg_write_addr),
/* */ .write_port1_data(ALU_O), /* */ .write_port1_data(ALU_O),

7
system/system.v
View File

@ -64,6 +64,7 @@ initial begin
end else end else
json_file_descriptor=0; json_file_descriptor=0;
`endif `endif
sane=0;
end end
//integer killswitch=0; //integer killswitch=0;
@ -132,8 +133,12 @@ always @(posedge clock) begin
endcase endcase
end end
always @(posedge reset)begin
sane<=1;
end
reg sane;
always @( ERROR ) begin always @( ERROR ) begin
if ( ERROR != `ERR_NO_ERROR ) begin if ( ERROR != `ERR_NO_ERROR && sane == 1 ) begin
$display("PROCESSOR RUN INTO AN ERROR."); $display("PROCESSOR RUN INTO AN ERROR.");
case (ERROR) case (ERROR)
default:begin default:begin