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Build system: Small fixes and corrected rebuild when only the verilator testbench was changed

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(Tim) Efthimis Kritikos 2023-12-09 02:39:14 +00:00
parent 65dfd21ef0
commit 3e66336456
4 changed files with 7 additions and 5 deletions
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2
common.mk
View File

@ -52,7 +52,7 @@ ifeq "${QUIET}" "1"
QUIET_CLEAN = @echo ' CLEAN '${PRINT_PATH_PREFIX};
QUIET_MRPROPER = @echo ' MRPROPER '${PRINT_PATH_PREFIX};
QUIET_VERILATOR_RUN = @printf ' %s %s\n' $1 $2;
QUIET_VERILATOR_RUN = @printf ' %s %s\n' $(shell basename "$1") $2;
Q = @
MAKEOPTS=--no-print-directory
.SILENT:

6
system/Makefile
View File

@ -87,6 +87,7 @@ ${VERILATOR_BIN}: ${VERILATOR_BIN}.mk
${VERILATOR_BIN}.mk: ${VERILATOR_TESTBENCH} ${SIMULATED_SOURCES}
${QUIET_VERILATOR}
mkdir -p ${BUILD_FILES_PREFIX}/sim_${FPGA_BOARD}/
rm -f ${VERILATOR_BIN}.mk # Verilator doesn't update this when just changing the testbench and the makefile breaks so we remove it to make sure
${Q}verilator -DCALCULATE_IPC -DOUTPUT_JSON_STATISTICS ${VERILATOR_OPTS} $^
${BUILD_FILES_PREFIX}/sim_${FPGA_BOARD}/${VERILATOR_FPGA_BIN}: ${BUILD_FILES_PREFIX}/sim_${FPGA_BOARD}/${VERILATOR_FPGA_BIN}.mk
@ -94,11 +95,12 @@ ${BUILD_FILES_PREFIX}/sim_${FPGA_BOARD}/${VERILATOR_FPGA_BIN}: ${BUILD_FILES_PRE
${BUILD_FILES_PREFIX}/sim_${FPGA_BOARD}/${VERILATOR_FPGA_BIN}.mk: fpga_config/${FPGA_BOARD}/testbench.cpp ${FPGA_SIM_SOURCES}
${QUIET_VERILATOR}
mkdir -p "${BUILD_FILES_PREFIX}/sim_${FPGA_BOARD}/"
mkdir -p "${BUILD_FILES_PREFIX}/sim_${FPGA_BOARD}/" # Verilator doesn't update this when just changing the testbench and the makefile breaks so we remove it to make sure
rm -f ${BUILD_FILES_PREFIX}/sim_${FPGA_BOARD}/${VERILATOR_FPGA_BIN}.mk
${Q}verilator -DCALCULATE_IPC -DOUTPUT_JSON_STATISTICS --Mdir ${BUILD_FILES_PREFIX}/sim_${FPGA_BOARD}/ ${VERILATOR_OPTS} ../../fpga_config/${FPGA_BOARD}/testbench.cpp ${FPGA_SIM_SOURCES}
.PHONY: fpga_sim
fpga_sim fpga_sim.fst: ${BUILD_FILES_PREFIX}/sim_${FPGA_BOARD}/${VERILATOR_FPGA_BIN} ${MICROCODE} simplified_ucode.txt ../boot_code/bios.stxt
fpga_sim fpga_sim.fst: ../boot_code/bios.stxt ${BUILD_FILES_PREFIX}/sim_${FPGA_BOARD}/${VERILATOR_FPGA_BIN} ${MICROCODE} simplified_ucode.txt
$(call QUIET_VERILATOR_RUN,$(word 2,$^),$<)
${Q} ${NUMACTL} "${BUILD_FILES_PREFIX}/sim_${FPGA_BOARD}/${VERILATOR_FPGA_BIN}" +VERSION=${VERSION} +WAVEFORM="fpga_sim.fst" +COMMIT=${COMMIT} +BOOT_CODE="../boot_code/bios.stxt" +MICROCODE="simplified_ucode.txt"

2
system/verilator_makefile_fpga
View File

@ -1,7 +1,7 @@
# This file is basically to make verilator compilation look pretty.
# If the project doesn't compile it might be because verilator handles compilation
# differently and this patch doesn't work anymore. In such case remove everything
# except the include Vsystem.mk line and try again.
# except the include Vfpga_top.mk line and try again.
VM_DEFAULT_RULES=0
include Vfpga_top.mk

2
tools/docker_build_tests.sh
View File

@ -21,7 +21,7 @@ do_test(){
SYSTEM_UPDATE="pacman --noconfirm -Sy make verilator xxd bin86 gcc python"
;;
esac
if tar c "$PROJDIRNAME" | docker run -i "$1" bash -c 'set -eu;tar x ;'"$SYSTEM_UPDATE"'; cd 9086; make clean; if [ "$(make -j boot_code/gnome_sort.run| tail -n5|head -n 1)" = "06 09 17 18 1F 21 33 37 3A 3F 44 4F 51 51 54 5D 8B 99 A5 AE DB DF E9 EE " ];then echo pass;else echo failed check; exit 1;fi ' > /dev/null 2>/dev/null
if tar c "$PROJDIRNAME" | docker run -i "$1" bash -c 'set -eu;tar x ;'"$SYSTEM_UPDATE"'; cd 9086; make mrproper; if [ "$(make -j boot_code/gnome_sort.run| tail -n5|head -n 1)" = "06 09 17 18 1F 21 33 37 3A 3F 44 4F 51 51 54 5D 8B 99 A5 AE DB DF E9 EE " ];then echo pass;else echo failed check; exit 1;fi ' > /dev/null 2>/dev/null
then
return 0
else