Added some documentation for the 8086 opcodes
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8086_documentation.md
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8086_documentation.md
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## ISA
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Instructions vary from 1 to 6 bytes.
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### Instructions format
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| 6bit | 1bit | 1bit | 2bit | 3bit | 3bit |
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| ---------------- | --------- | ---- | ---- | ---- | ---- |
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| Opcode | D bit | W bit | MOD | REG | R/M |
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* **D**-bit : the register specified in the Register ID field is a source register (D = 0) or destination register (D =1).
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* **W**-bit : specifies whether the instruction is a byte instruction (W = 0) or a word instruction (W = 1).
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On some instructions:
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* **S**-bit : An 8-bit 2’s complement number. It can be extended to a 16-bit 2’s complement number depending on the W-bit by making all of the bits in the higher-order byte equal the most significant bit in the low order byte. This is known as sign extension.
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| S | W | Operation |
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| --- | --- | -------------- |
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| 0 | 0 | 8bit operation |
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| 0 | 1 | 16bit operation with 16bit immediate operand |
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| 1 | 0 | invalid? |
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| 1 | 1 | 16bit operation with a sign extended 8bit immediate operand
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* **V**-bit : V-bit decides the number of shifts for rotate and shift instructions. If V = 0, then count = 1; if V = 1, the count is in CL register. For example, if V = 1 and CL = 2 then shift or rotate instruction shifts or rotates 2-bits
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* **Z**-bit : Used as a compare bit with the zero flag in conditional repeat and loop instructions. ex branch if zero is set or clear.
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| Register ID / REG | Register Name |
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|:-------------------:|:-------------:|
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| 0 0 0 | AL AX |
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| 0 0 1 | CL CX |
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| 0 1 0 | DL DX |
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| 0 1 1 | BL BX |
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| 1 0 0 | AH SP |
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| 1 0 1 | CH BP |
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| 1 1 0 | DH SI |
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| 1 1 1 | BH DI |
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The second byte of the instruction usually identifies the instruction's operands. The **MOD** (mode) field weather on of the operands is in memory or if both are registers. In some instructions like the immediate-to-memory type the **REG** field is used as an extension of the opcode. The encoding of **R/M** depends on how MOD is set. if MOD=11 (register-register mode) then **R/M** specifies the second Register using the Register ID. otherwise it specifies how the effective address in memory is calculated
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|R/M | Memory Mode with no displacement [ 0 0 ] | Memory mode with 8 bit displacement [ 0 1 ] | Memory Mode with 16 bit displacement [ 1 0 ] | Register Mode [ 1 1 ] W = 0| Register Mode [ 1 1 ] W = 1 |
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|---- | ---------------------------------------- | ------------------------------------------- | -------------------------------------------- | --------------------------- | --------------------------- |
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|000 | [BX] + [SI] | [BX] + [SI] + d8 | [BX] + [SI] + d16 | AL | AX |
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|001 | [BX] + [DI] | [BX] + [DI] + d8 | [BX] + [DI] + d16 | CL | CX |
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|010 | [BP] + [SI] | [BP] + [SI] + d8 | [BP] + [SI] + d16 | DL | DX |
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|011 | [BP] + [DI] | [BP] + [DI] + d8 | [BP] + [DI] + d16 | BL | BX |
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|100 | [SI] | [SI] + d8 | [SI] + d16 | AH | SP |
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|101 | [DI] | [DI] + d8 | [DI] + d16 | CH | BP |
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|110 | d16 (direct) | [BP] + d8 | [BP] + d16 | DH | SI |
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|111 | [BX] | [BX] + d8 | [BX] + d16 | BH | DI |
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8086_documentation.md.bak
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50
8086_documentation.md.bak
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## ISA
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Instructions vary from 1 to 6 bytes.
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### Instructions format
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| 6bit | 1bit | 1bit | 2bit | 3bit | 3bit |
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| ---------------- | --------- | ---- | ---- | ---- | ---- |
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| Opcode | D bit | W bit | MOD | REG | R/M |
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* **D**-bit : the register specified in the Register ID field is a source register (D = 0) or destination register (D =1).
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* **W**-bit : specifies whether the instruction is a byte instruction (W = 0) or a word instruction (W = 1).
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On some instructions:
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* **S**-bit : An 8-bit 2’s complement number. It can be extended to a 16-bit 2’s complement number depending on the W-bit by making all of the bits in the higher-order byte equal the most significant bit in the low order byte. This is known as sign extension.
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| S | W | Operation |
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| --- | --- | -------------- |
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| 0 | 0 | 8bit operation |
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| 0 | 1 | 16bit operation with 16bit immediate operand |
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| 1 | 0 | invalid? |
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| 1 | 1 | 16bit operation with a sign extended 8bit immediate operand
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* **V**-bit : V-bit decides the number of shifts for rotate and shift instructions. If V = 0, then count = 1; if V = 1, the count is in CL register. For example, if V = 1 and CL = 2 then shift or rotate instruction shifts or rotates 2-bits
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* **Z**-bit : Used as a compare bit with the zero flag in conditional repeat and loop instructions. ex branch if zero is set or clear.
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| Register ID / REG | Register Name |
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|:-------------------:|:-------------:|
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| 0 0 0 | AL AX |
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| 0 0 1 | CL CX |
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| 0 1 0 | DL DX |
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| 0 1 1 | BL BX |
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| 1 0 0 | AH SP |
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| 1 0 1 | CH BP |
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| 1 1 0 | DH SI |
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| 1 1 1 | BH DI |
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The second byte of the instruction usually identifies the insturction's operands. The **MOD** (mode) field weather on of the operands is in memory or if both are registers. In some instructions like the immediate-to-memory type the **REG** field is used as an extension of the opcode. The encoding of **R/M** depends on how MOD is set. if MOD=11 (register-register mode) then **R/M** specifies the second Register using the Register ID. otherwise it specifies how the effective address in memory is calculated
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Some instructions have the following
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|R/M | Memory Mode with no displacement [ 0 0 ] | Memory mode with 8 bit displacement [ 0 1 ] | Memory Mode with 16 bit displacement [ 1 0 ] | Register Mode [ 1 1 ] W = 0| Register Mode [ 1 1 ] W = 1 |
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|---- | ---------------------------------------- | ------------------------------------------- | -------------------------------------------- | --------------------------- | --------------------------- |
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|000 | [BX] + [SI] | [BX] + [SI] + d8 | [BX] + [SI] + d16 | AL | AX |
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|001 | [BX] + [DI] | [BX] + [DI] + d8 | [BX] + [DI] + d16 | CL | CX |
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|010 | [BP] + [SI] | [BP] + [SI] + d8 | [BP] + [SI] + d16 | DL | DX |
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|011 | [BP] + [DI] | [BP] + [DI] + d8 | [BP] + [DI] + d16 | BL | BX |
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|100 | [SI] | [SI] + d8 | [SI] + d16 | AH | SP |
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|101 | [DI] | [DI] + d8 | [DI] + d16 | CH | BP |
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|110 | d16 (direct) | [BP] + d8 | [BP] + d16 | DH | SI |
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|111 | [BX] | [BX] + d8 | [BX] + d16 | BH | DI |
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BIN
cpu/.processor.v.swp
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cpu/.processor.v.swp
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