From 361d98b7e6dc5893117b3d3f85a22a680096116f Mon Sep 17 00:00:00 2001 From: "(Tim) Efthimis Kritikos" Date: Wed, 8 Feb 2023 20:51:56 +0000 Subject: [PATCH] Added some documentation for the 8086 opcodes --- 8086_documentation.md | 48 ++++++++++++++++++++++++++++++++++++ 8086_documentation.md.bak | 50 ++++++++++++++++++++++++++++++++++++++ cpu/.processor.v.swp | Bin 0 -> 12288 bytes 3 files changed, 98 insertions(+) create mode 100644 8086_documentation.md create mode 100644 8086_documentation.md.bak create mode 100644 cpu/.processor.v.swp diff --git a/8086_documentation.md b/8086_documentation.md new file mode 100644 index 0000000..5666c0d --- /dev/null +++ b/8086_documentation.md @@ -0,0 +1,48 @@ +## ISA +Instructions vary from 1 to 6 bytes. + +### Instructions format +| 6bit | 1bit | 1bit | 2bit | 3bit | 3bit | +| ---------------- | --------- | ---- | ---- | ---- | ---- | +| Opcode | D bit | W bit | MOD | REG | R/M | + +* **D**-bit : the register specified in the Register ID field is a source register (D = 0) or destination register (D =1). +* **W**-bit : specifies whether the instruction is a byte instruction (W = 0) or a word instruction (W = 1). + +On some instructions: + +* **S**-bit : An 8-bit 2’s complement number. It can be extended to a 16-bit 2’s complement number depending on the W-bit by making all of the bits in the higher-order byte equal the most significant bit in the low order byte. This is known as sign extension. + +| S | W | Operation | +| --- | --- | -------------- | +| 0 | 0 | 8bit operation | +| 0 | 1 | 16bit operation with 16bit immediate operand | +| 1 | 0 | invalid? | +| 1 | 1 | 16bit operation with a sign extended 8bit immediate operand + +* **V**-bit : V-bit decides the number of shifts for rotate and shift instructions. If V = 0, then count = 1; if V = 1, the count is in CL register. For example, if V = 1 and CL = 2 then shift or rotate instruction shifts or rotates 2-bits +* **Z**-bit : Used as a compare bit with the zero flag in conditional repeat and loop instructions. ex branch if zero is set or clear. + +| Register ID / REG | Register Name | +|:-------------------:|:-------------:| +| 0 0 0 | AL AX | +| 0 0 1 | CL CX | +| 0 1 0 | DL DX | +| 0 1 1 | BL BX | +| 1 0 0 | AH SP | +| 1 0 1 | CH BP | +| 1 1 0 | DH SI | +| 1 1 1 | BH DI | + +The second byte of the instruction usually identifies the instruction's operands. The **MOD** (mode) field weather on of the operands is in memory or if both are registers. In some instructions like the immediate-to-memory type the **REG** field is used as an extension of the opcode. The encoding of **R/M** depends on how MOD is set. if MOD=11 (register-register mode) then **R/M** specifies the second Register using the Register ID. otherwise it specifies how the effective address in memory is calculated + +|R/M | Memory Mode with no displacement [ 0 0 ] | Memory mode with 8 bit displacement [ 0 1 ] | Memory Mode with 16 bit displacement [ 1 0 ] | Register Mode [ 1 1 ] W = 0| Register Mode [ 1 1 ] W = 1 | +|---- | ---------------------------------------- | ------------------------------------------- | -------------------------------------------- | --------------------------- | --------------------------- | +|000 | [BX] + [SI] | [BX] + [SI] + d8 | [BX] + [SI] + d16 | AL | AX | +|001 | [BX] + [DI] | [BX] + [DI] + d8 | [BX] + [DI] + d16 | CL | CX | +|010 | [BP] + [SI] | [BP] + [SI] + d8 | [BP] + [SI] + d16 | DL | DX | +|011 | [BP] + [DI] | [BP] + [DI] + d8 | [BP] + [DI] + d16 | BL | BX | +|100 | [SI] | [SI] + d8 | [SI] + d16 | AH | SP | +|101 | [DI] | [DI] + d8 | [DI] + d16 | CH | BP | +|110 | d16 (direct) | [BP] + d8 | [BP] + d16 | DH | SI | +|111 | [BX] | [BX] + d8 | [BX] + d16 | BH | DI | diff --git a/8086_documentation.md.bak b/8086_documentation.md.bak new file mode 100644 index 0000000..65da2fa --- /dev/null +++ b/8086_documentation.md.bak @@ -0,0 +1,50 @@ +## ISA +Instructions vary from 1 to 6 bytes. + +### Instructions format +| 6bit | 1bit | 1bit | 2bit | 3bit | 3bit | +| ---------------- | --------- | ---- | ---- | ---- | ---- | +| Opcode | D bit | W bit | MOD | REG | R/M | + +* **D**-bit : the register specified in the Register ID field is a source register (D = 0) or destination register (D =1). +* **W**-bit : specifies whether the instruction is a byte instruction (W = 0) or a word instruction (W = 1). + +On some instructions: + +* **S**-bit : An 8-bit 2’s complement number. It can be extended to a 16-bit 2’s complement number depending on the W-bit by making all of the bits in the higher-order byte equal the most significant bit in the low order byte. This is known as sign extension. + +| S | W | Operation | +| --- | --- | -------------- | +| 0 | 0 | 8bit operation | +| 0 | 1 | 16bit operation with 16bit immediate operand | +| 1 | 0 | invalid? | +| 1 | 1 | 16bit operation with a sign extended 8bit immediate operand + +* **V**-bit : V-bit decides the number of shifts for rotate and shift instructions. If V = 0, then count = 1; if V = 1, the count is in CL register. For example, if V = 1 and CL = 2 then shift or rotate instruction shifts or rotates 2-bits +* **Z**-bit : Used as a compare bit with the zero flag in conditional repeat and loop instructions. ex branch if zero is set or clear. + +| Register ID / REG | Register Name | +|:-------------------:|:-------------:| +| 0 0 0 | AL AX | +| 0 0 1 | CL CX | +| 0 1 0 | DL DX | +| 0 1 1 | BL BX | +| 1 0 0 | AH SP | +| 1 0 1 | CH BP | +| 1 1 0 | DH SI | +| 1 1 1 | BH DI | + +The second byte of the instruction usually identifies the insturction's operands. The **MOD** (mode) field weather on of the operands is in memory or if both are registers. In some instructions like the immediate-to-memory type the **REG** field is used as an extension of the opcode. The encoding of **R/M** depends on how MOD is set. if MOD=11 (register-register mode) then **R/M** specifies the second Register using the Register ID. otherwise it specifies how the effective address in memory is calculated + +Some instructions have the following + +|R/M | Memory Mode with no displacement [ 0 0 ] | Memory mode with 8 bit displacement [ 0 1 ] | Memory Mode with 16 bit displacement [ 1 0 ] | Register Mode [ 1 1 ] W = 0| Register Mode [ 1 1 ] W = 1 | +|---- | ---------------------------------------- | ------------------------------------------- | -------------------------------------------- | --------------------------- | --------------------------- | +|000 | [BX] + [SI] | [BX] + [SI] + d8 | [BX] + [SI] + d16 | AL | AX | +|001 | [BX] + [DI] | [BX] + [DI] + d8 | [BX] + [DI] + d16 | CL | CX | +|010 | [BP] + [SI] | [BP] + [SI] + d8 | [BP] + [SI] + d16 | DL | DX | +|011 | [BP] + [DI] | [BP] + [DI] + d8 | [BP] + [DI] + d16 | BL | BX | +|100 | [SI] | [SI] + d8 | [SI] + d16 | AH | SP | +|101 | [DI] | [DI] + d8 | [DI] + d16 | CH | BP | +|110 | d16 (direct) | [BP] + d8 | [BP] + d16 | DH | SI | +|111 | [BX] | [BX] + d8 | [BX] + d16 | BH | DI | diff --git a/cpu/.processor.v.swp b/cpu/.processor.v.swp new file mode 100644 index 0000000000000000000000000000000000000000..a3ef2a5eecee8afe4c35945be39d497135c38d6d GIT binary patch literal 12288 zcmeI2PiP!f9LHZh)Q+_(tx&xEG*Xi`+1cH;>7N*AOrj08Mzcw46v`7^!h~mxfdo#1yZMXESyn)YdX6E;P z@Avz@-|r1eX0?1`;W!;Cl^Ko)7`yn+FYccgH?hBeWGs!jRG05`D7%STM@Vm?vVUTx zQeBxFI^=a_Xs?AxrB+otleA0i(d36-blD#KCPVd#e@Q>LZUlOgpx(+dhqkvJs zC}0#Y3K#|cHwq-tCUzFt+?8kK=ii%d`p!?ymr=kdU=%P47zK<1MggOMQNSo*6fg=H z1&jj!K?NL-v7MV4`~GeOkN^J{zyE)~pRwP-WpD|c2QgRxN5O;O#(j)^2|fmIfj2=4 z63_svzyUL0FBk^tx|xCq_`uYoQ&4Gw^<;Mc8;eG9$@ zUx81+2jDE|g43W4TEGRT!1LfF_~IVMJ_8rPIdBGafe&inAUFUf!J}X^xM4B&1Na7f z3O)iKg7e^ga1OiyJTMCmfXBcV@Yfc`{s7m(HEf1J_UH_wS|`koH6{#Ed611q@Qqle3~j#%(5hR zJatl5C;W86W#|NT$MYoKx2vzFvAX%J6wO(Yh6#-P293svlkn;3@))i1rXMmV=s4Y& zj$}8AtM+a+Fne#0Fr>+2+HDWS;)ih}Q#bKNSa0~DAGf$StwKSl#DkdU6Ij+zOO-)i zJk?_6;qml~kV#=>iRjNgS`OvS4TQT!yLPFVWimZoDcs%~l^#htV!tsuEXI5+ZD2qmFM_)vHmkM0WettUVLYNgUM`<9%*a3k~?y9X2+FPDGjI z9jFSr=s-7EBi(VTcuWDhhvmq)@|Bp`2p8mD3dzOizR}i zjlp?e3|jOWqbLZiaK8`RCYgrh#1x3IslJm|UaK)Vl2ek(kb5M;5`*oG+w%E3CofI9 zJlew&j69Rk#8((>btt$_4__(#+hf|$LaJC^mI3NBOY z*7m!tb+Iw<&{++5p-+)L_4*;ZPeM{r^MfOhp%Vn6Lmbu6Y-K4Vf?Uy#kOkCG;$)?t zCmV6;3r}g|3bcfqkjDe3OASn-twq@Io2i64QOk*WiB7h7hzV4r#|oJ#S=oUMfR}3W}Wy>knhi!a3QJ*iR8>5wSxm2bJnp;^uHD+gL zyL0<~>k!7u=JqC$2a`&vY(Kd){~UsWFLg|jrPnxI=Mv>CsEvA#9O<-C7gGB~+3trO z4p>53l!l8v5)VS^v((Ay3g58wcvEs7_gU%55r>{R_jmLK{8ZEr_^kHoO%xKILTZ1@ bR(xPvf;wtbdRg^h>^i8nN*LRfC}#fxZJ7CN literal 0 HcmV?d00001