Efthimis/9086
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Added simple support for \n and \r on the HD44780 driver, increased the synthesised mem to fit brainfuck_compiled.asm and made it the default.

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(Tim) Efthimis Kritikos 2023-11-12 21:39:27 +00:00
parent 189b037bdf
commit 2c8e8a9d9c
6 changed files with 64 additions and 26 deletions
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2
Makefile
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@ -48,5 +48,5 @@ clean:
${Q}make ${MAKEOPTS} -C system clean ${Q}make ${MAKEOPTS} -C system clean
${Q}make ${MAKEOPTS} -C boot_code clean ${Q}make ${MAKEOPTS} -C boot_code clean
upload: boot_code/gnome_sort.txt upload: boot_code/brainfuck_compiled.txt
make -C system upload make -C system upload

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boot_code/brainfuck_mandelbrot.fst.hier Normal file
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4
system/Makefile
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@ -75,9 +75,9 @@ simplified_ucode.txt:ucode.txt
${Q}tr 'x' '0' < $^ | sed 's@//.*@@' | grep ^@ |sort | sed 's/.* .//;s/ $$//' | tr -d _ > $@ ${Q}tr 'x' '0' < $^ | sed 's@//.*@@' | grep ^@ |sort | sed 's/.* .//;s/ $$//' | tr -d _ > $@
#TODO: we are relying on yosys to trim the input program txt file and hope its enough for the whole program... #TODO: we are relying on yosys to trim the input program txt file and hope its enough for the whole program...
synth_ecp5.json: ${SOURCES} ${TOP_LEVEL_SOURCE} fpga_config/${FPGA_BOARD}/fpga_top.v ${EXTRA_SYNTHESIS_SOURCES} ${INCLUDES} ../boot_code/gnome_sort.txt simplified_ucode.txt synth_ecp5.json: ${SOURCES} ${TOP_LEVEL_SOURCE} fpga_config/${FPGA_BOARD}/fpga_top.v ${EXTRA_SYNTHESIS_SOURCES} ${INCLUDES} ../boot_code/brainfuck_compiled.txt simplified_ucode.txt
${QUIET_YOSYS} ${QUIET_YOSYS}
${Q} yosys -q -D BUILTIN_RAM=512 -D NOT_FULL -p 'read -sv '"${SOURCES} ${TOP_LEVEL_SOURCE} fpga_config/${FPGA_BOARD}/fpga_top.v ${EXTRA_SYNTHESIS_SOURCES} ; synth_ecp5 -json $@ -top fpga_top" ${Q} yosys -q -D BUILTIN_RAM=2048 -D NOT_FULL -p 'read -sv '"${SOURCES} ${TOP_LEVEL_SOURCE} fpga_config/${FPGA_BOARD}/fpga_top.v ${EXTRA_SYNTHESIS_SOURCES} ; synth_ecp5 -json $@ -top fpga_top"
synth_ecp5_out.config:synth_ecp5.json synth_ecp5_out.config:synth_ecp5.json
${QUIET_NEXTPNR} ${QUIET_NEXTPNR}

3
system/fpga_config/OrangeCrab_r0.2.1/fpga_top.v
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@ -39,8 +39,9 @@ wire [19:0] address_bus;
wire [15:0] data_bus_read,data_bus_write; wire [15:0] data_bus_read,data_bus_write;
wire rd,wr,BHE,IOMEM; wire rd,wr,BHE,IOMEM;
system system( system system(
/* MISC */ counter[7],reset /* MISC */ counter[9],reset
/* MEMORY / IO */ ,address_bus,data_bus_read,data_bus_write,BHE,rd,wr,IOMEM,HALT,ERROR /* MEMORY / IO */ ,address_bus,data_bus_read,data_bus_write,BHE,rd,wr,IOMEM,HALT,ERROR
); );

2
system/memory.v
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@ -34,7 +34,7 @@ initial begin
$readmemh(boot_code, memory,0,`BUILTIN_RAM-1); $readmemh(boot_code, memory,0,`BUILTIN_RAM-1);
`else `else
//TODO: don't have it hard coded //TODO: don't have it hard coded
$readmemh("../boot_code/gnome_sort.txt", memory,0,`BUILTIN_RAM-1); $readmemh("../boot_code/brainfuck_compiled.txt", memory,0,`BUILTIN_RAM-1);
`endif `endif
`ifdef NOT_FULL `ifdef NOT_FULL

79
system/peripherals/ascii_to_HD44780_driver.v
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@ -68,6 +68,8 @@ reg [5:0]col=0;
reg [7:0] driver_state =0; reg [7:0] driver_state =0;
reg next_line;
always @(posedge clock,negedge rst_n) begin always @(posedge clock,negedge rst_n) begin
if(rst_n==0)begin if(rst_n==0)begin
in_data_ready<=0; in_data_ready<=0;
@ -102,11 +104,26 @@ always @(posedge clock,negedge rst_n) begin
cmd_data<=1'b0; cmd_data<=1'b0;
data_write_wait_counter<=6'd50; data_write_wait_counter<=6'd50;
driver_state<=8'd2; driver_state<=8'd2;
next_line<=1;
end else if(data_write_req==1)begin end else if(data_write_req==1)begin
cmd_data<=1'b1; if(in_ascii_data==8'h0a)begin
print_data<=in_ascii_data; data<=4'hf;
cmd_data<=1'b0;
write_req<=1'b1;
driver_state<=8'd2;
next_line<=1;
end else if(in_ascii_data==8'h0d)begin
data<=4'hf;
cmd_data<=1'b0;
write_req<=1'b1;
driver_state<=8'd2;
next_line<=0;
end else begin
cmd_data<=1'b1;
print_data<=in_ascii_data;
driver_state<=8'd9;
end
in_data_ready<=0; in_data_ready<=0;
driver_state<=8'd9;
end else begin end else begin
in_data_ready<=1; in_data_ready<=1;
end end
@ -148,12 +165,21 @@ always @(posedge clock,negedge rst_n) begin
driver_state<=8'd6; driver_state<=8'd6;
end end
8'd6:begin 8'd6:begin
case(line) if(next_line)begin
2'd0: data<=4'hC; case(line)
2'd1: data<=4'h9; 2'd0: data<=4'hC;
2'd2: data<=4'hD; 2'd1: data<=4'h9;
2'd3: data<=4'hD; 2'd2: data<=4'hD;
endcase 2'd3: data<=4'hD;
endcase
end else begin
case(line)
2'd0: data<=4'h0;
2'd1: data<=4'hC;
2'd2: data<=4'h9;
2'd3: data<=4'hD;
endcase
end
data_write_wait_counter<=6'd50; data_write_wait_counter<=6'd50;
if(!done_writing)begin if(!done_writing)begin
driver_state<=8'd7; driver_state<=8'd7;
@ -166,24 +192,35 @@ always @(posedge clock,negedge rst_n) begin
driver_state<=8'd8; driver_state<=8'd8;
end end
8'd8:begin 8'd8:begin
case(line) if(next_line)begin
2'd0: begin data<=4'h0; ; end case(line)
2'd1: begin data<=4'h4; ; end 2'd0: begin data<=4'h0; ; end
2'd2: begin data<=4'h4; ; end 2'd1: begin data<=4'h4; ; end
2'd3: begin data<=4'h4; ; end 2'd2: begin data<=4'h4; ; end
endcase 2'd3: begin data<=4'h4; ; end
endcase
end else begin
case(line)
2'd0: begin data<=4'h0; ; end
2'd1: begin data<=4'h0; ; end
2'd2: begin data<=4'h4; ; end
2'd3: begin data<=4'h4; ; end
endcase
end
cmd_data<=1'b0; cmd_data<=1'b0;
data_write_wait_counter<=6'd50; data_write_wait_counter<=6'd50;
if(!done_writing)begin if(!done_writing)begin
driver_state<=8'd0; driver_state<=8'd0;
col<=0; col<=0;
write_req<=1'b0; write_req<=1'b0;
case(line) if(next_line)begin
2'd0: begin line<=1; end case(line)
2'd1: begin line<=2; end 2'd0: begin line<=1; end
2'd2: begin line<=3; end 2'd1: begin line<=2; end
2'd3: begin line<=3; end 2'd2: begin line<=3; end
endcase 2'd3: begin line<=3; end
endcase
end
end else end else
write_req<=1'b1; write_req<=1'b1;
end end