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Project: Cleaned up some code and run the project through aspell

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This commit is contained in:
(Tim) Efthimis Kritikos 2023-11-15 14:37:46 +00:00
parent 98d30a1813
commit 29bc2e6d96
13 changed files with 66 additions and 77 deletions
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6
README.md
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@ -28,10 +28,10 @@ This list shows the software needed and the versions used during development :
After that you can run `make` on the top level directory and it should build everything and start the simulation
### Synthesis and bitstream creation ( for FPGAs )
Synthesis is based on Yosys. You need to set FPGA\_BOARD in [./common.mk](./common.mk) to the name of a directory inside [./system/fpga\_config/](system/fpga_config/). You should also check inside your board directory for config.mk for further board-specific configuration options. Then you can run `make upload` in the top level directory and it should create the bitstream and upload it.
### Synthesis and bitstream creation for FPGAs
You need to set FPGA\_BOARD in [./common.mk](./common.mk) to the name of a directory inside [./system/fpga\_config/](system/fpga_config/). You should also check inside your board directory for config.mk for further board-specific configuration options. Then you can run `make upload` in the top level directory and it should create the bitstream and upload it.
These are the currently supported fpga boards:
These are the currently supported FPGA boards:
* OrangeCrab r0.2.1

4
system/Makefile
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@ -46,14 +46,14 @@ VERILATOR_OPTS += -x-assign fast --x-initial fast
# COMPILING
${SYSTEM_VVP} : ${TOP_LEVEL_SOURCE} ${SOURCES} ${INCLUDES} ${EVENT_SIM_TESTBENCH}
${QUIET_IVERILOG}
${Q}iverilog -g2012 -DBUILTIN_RAM=32768 -D CALCULATE_IPC -D OTUPUT_JSON_STATISTICS -o "$@" ${TOP_LEVEL_SOURCE} ${SOURCES} ${EVENT_SIM_TESTBENCH}
${Q}iverilog -g2012 -DBUILTIN_RAM=32768 -D CALCULATE_IPC -D OUTPUT_JSON_STATISTICS -o "$@" ${TOP_LEVEL_SOURCE} ${SOURCES} ${EVENT_SIM_TESTBENCH}
${VERILATOR_BIN}: ${VERILATOR_BIN}.mk
${Q}make ${MAKEOPTS} OPT_FAST="-O2 -march=native -mtune=native" -C obj_dir -f ../verilator_makefile Vsystem
${VERILATOR_BIN}.mk: ${VERILATOR_TESTBENCH} ${TOP_LEVEL_SOURCE} ${SOURCES} ${INCLUDES}
${QUIET_VERILATOR}
${Q}verilator -DBUILTIN_RAM=32768 -UNOT_FULL -DCALCULATE_IPC -DOTUPUT_JSON_STATISTICS ${VERILATOR_OPTS} $^
${Q}verilator -DBUILTIN_RAM=32768 -UNOT_FULL -DCALCULATE_IPC -DOUTPUT_JSON_STATISTICS ${VERILATOR_OPTS} $^
include fpga_config/${FPGA_BOARD}/config.mk

15
system/biu.v
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@ -58,26 +58,26 @@ module BIU (
/* */ ,input jump_req, input write_request, input read_request
/* */ ,input[15:0] ADDRESS_INPUT, input [15:0] DATA_EX_WRITE
/**************** OTUPUT TO EX *****************/
/**************** OUTPUT TO EX *****************/
/* */ ,output [15:0] DATA_EX_READ
`ifdef OTUPUT_JSON_STATISTICS
`ifdef OUTPUT_JSON_STATISTICS
/***************** STATISTICS *****************/
/* */ ,output wire [`L1_CACHE_SIZE-1:0] FIFO_SIZE_STAT, output wire VALID_INSTRUCTION_STAT
`endif
);
`ifdef OTUPUT_JSON_STATISTICS
`ifdef OUTPUT_JSON_STATISTICS
assign FIFO_SIZE_STAT = FIFO_SIZE;
assign VALID_INSTRUCTION_STAT = ((Isit1==1) && (FIFO_SIZE!=0) && `EARLY_VALID_INSTRUCTION_) || ((fifoIsize==2) && (FIFO_SIZE > 1) && `EARLY_VALID_INSTRUCTION_) || ((fifoIsize==3) && (FIFO_SIZE > 2) && `EARLY_VALID_INSTRUCTION_) || (FIFO_SIZE>3);
`endif
reg [15:0] data_bus_output_register;
assign external_data_bus_write=data_bus_output_register; //TODO: should we rename
assign external_data_bus_write=data_bus_output_register; //TODO: should we rename?
reg [15:0] DATA_OUT;
assign DATA_EX_READ=DATA_OUT; //TODO should we ranme
assign DATA_EX_READ=DATA_OUT; //TODO should we rename?
`define FIFO_SIZE_BYTES $rtoi($pow(2,`L1_CACHE_SIZE))
@ -172,7 +172,6 @@ always @(posedge clock) begin
end
/*************** DATA WRITE ***************/
//TODO TODO TODO flush fifo, self modifying code
`BIU_PUT_UNALIGNED_16BIT_DATA:begin
`ifdef DEBUG_DATA_READ_WRITES
$display("Writing 16bit %04x at %04x",DATA_EX_WRITE,DATA_ADDRESS);
@ -351,7 +350,7 @@ always @( posedge clock) begin
VALID_INSTRUCTION <= 0;
`else
if(FIFO_start==FIFO_end) begin
/*TODO: Same as on the first statment on the other side of the `ifdef */
/*TODO: Same as on the first statement on the other side of the `ifdef */
VALID_INSTRUCTION <= 0;
end else if(FIFO_SIZE>`L1_CACHE_SIZE'd3)begin
VALID_INSTRUCTION <= 1;
@ -369,7 +368,7 @@ end
wire [2:0] Isize;
InstrSize InstrSize({INSTRUCTION[31:24],INSTRUCTION[21:19]},Isize);
`ifdef INCLUDE_EARLY_CALC_CIRUIT
`ifdef INCLUDE_EARLY_CALC_CIRCUIT
wire [2:0] fifoIsize;
wire Isit1;
InstrSize fifoInstrSize({INPUT_FIFO[FIFO_start][7:0],INPUT_FIFO[FIFO_start+`L1_CACHE_SIZE'd1][5:3]},fifoIsize);

10
system/config.v
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@ -25,7 +25,7 @@
/** OUTPUT **/
/* These are usually set at build time*/
//`define CALCULATE_IPC
//`define OTUPUT_JSON_STATISTICS
//`define OUTPUT_JSON_STATISTICS
/** Optimisations **/
@ -62,10 +62,10 @@
`undef DEBUG_PC_ADDRESS
`undef DEBUG_DATA_READ_WRITES
`undef CALCULATE_IPC
`undef OTUPUT_JSON_STATISTICS
`undef OUTPUT_JSON_STATISTICS
`endif
`ifdef OTUPUT_JSON_STATISTICS
`ifdef OUTPUT_JSON_STATISTICS
`define CALCULATE_IPC
`endif
@ -75,12 +75,12 @@
`endif
`ifdef EARLY_VALID_INSTRUCTION
`define INCLUDE_EARLY_CALC_CIRUIT
`define INCLUDE_EARLY_CALC_CIRCUIT
`define EARLY_VALID_INSTRUCTION_ 1
`else
`define EARLY_VALID_INSTRUCTION_ 0
`endif
`ifdef CALCULATE_IPC
`define INCLUDE_EARLY_CALC_CIRUIT
`define INCLUDE_EARLY_CALC_CIRCUIT
`endif

56
system/decoder.v
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@ -98,10 +98,6 @@ InstrSize InstrSize({IF2DE_INSTRUCTION[31:24],IF2DE_INSTRUCTION[21:19]},instr_en
reg owe_set_init;
//TODO: Why do we need to make a local copy on a register for the code inside the always @(next_state) to read it?
// For some reason the raw VALID_INSTRUCTION signal reads always 1 and it has something to do with the block
// being triggered by next_exec
reg [1:0] wait_;
always @(posedge clock)begin
@ -254,12 +250,6 @@ microcode ucode(seq_addr_input,ucode_data);
`define invalid_instruction next_state=`EXEC_WAIT;ERROR<=`ERR_UNIMPL_INSTRUCTION;HALT<=0;IN_MOD=3'b011;seq_addr_entry<=`UCODE_NO_INSTRUCTION;opcode_size=0;DEPENDS_ON_PREVIOUS<=0;
`define unimpl_addressing_mode next_state=`EXEC_WAIT;ERROR <= `ERR_UNIMPL_ADDRESSING_MODE;HALT<=0;IN_MOD=3'b011;seq_addr_entry<=`UCODE_NO_INSTRUCTION;
//TODO: A possible optimisation for instruction with 8bit parameter and
//opcode_size=0 would be to set PARAM1 here instead of sending execution over
//to EXEC_DE_LOAD_8_PARAM
`define normal_instruction seq_addr_entry<=`UCODE_NO_INSTRUCTION;ERROR<=`ERR_NO_ERROR;HALT<=0;MEM_OR_IO<=0;
`define normal_microcoded ERROR<=`ERR_NO_ERROR;HALT<=0;MEM_OR_IO<=0;
@ -300,7 +290,7 @@ always @( posedge clock ) begin
else
PARAM_ACTION=`LOAD_8;
DEPENDS_ON_PREVIOUS<=0;
`normal_instruction;
`normal_instruction
end
11'b1000_00??_101, /* SUB */
11'b1000_00??_000 : /* ADD */ begin
@ -344,7 +334,7 @@ always @( posedge clock ) begin
end
endcase
DEPENDS_ON_PREVIOUS<=0;
`normal_instruction;
`normal_instruction
end
11'b1000_00??_111 : begin
/* CMP - compare Immediate with register / memory */
@ -379,7 +369,7 @@ always @( posedge clock ) begin
else
PARAM_ACTION=`LOAD_8;
DEPENDS_ON_PREVIOUS<=0;
`normal_instruction;
`normal_instruction
end
11'b1011_????_??? : begin
/* MOV - Move Immediate byte to register */
@ -399,7 +389,7 @@ always @( posedge clock ) begin
PARAM2=0;
ALU_OP<=`ALU_OP_ADD;
next_state=`EXEC_WRITE_ENTRY;
`normal_instruction;
`normal_instruction
DEPENDS_ON_PREVIOUS<=0;
memio_address_select=0;
end
@ -445,7 +435,7 @@ always @( posedge clock ) begin
end
ALU_OP<=`ALU_OP_ADD;
`normal_instruction;
`normal_instruction
DEPENDS_ON_PREVIOUS<=0;
memio_address_select=0;
end
@ -469,7 +459,7 @@ always @( posedge clock ) begin
else
ALU_OP<=`ALU_OP_SUB;
next_state=`EXEC_WRITE_ENTRY;
`normal_instruction;
`normal_instruction
DEPENDS_ON_PREVIOUS<=0;
memio_address_select=0;
end
@ -497,7 +487,7 @@ always @( posedge clock ) begin
next_state=`EXEC_WRITE_ENTRY;
else
next_state=`EXEC_MEMIO_READ;
`normal_instruction;
`normal_instruction
DEPENDS_ON_PREVIOUS<=0;
memio_address_select=0;
end
@ -544,7 +534,7 @@ always @( posedge clock ) begin
//PARAM1[7:0]=INSTRUCTION[7:0]; TODO:needed?
end
next_state=`EXEC_WRITE_ENTRY;
`normal_instruction;
`normal_instruction
DEPENDS_ON_PREVIOUS<=0;
memio_address_select=0;
end
@ -573,7 +563,7 @@ always @( posedge clock ) begin
else begin
next_state=`EXEC_WRITE_ENTRY;
end
`normal_instruction;
`normal_instruction
end
3'b010: begin
/* Jump on (not) Zero */
@ -581,7 +571,7 @@ always @( posedge clock ) begin
next_state=`EXEC_NEXT_INSTRUCTION;
else
next_state=`EXEC_WRITE_ENTRY;
`normal_instruction;
`normal_instruction
end
3'b100: begin
/* Jump on (not) Sign */
@ -589,7 +579,7 @@ always @( posedge clock ) begin
next_state=`EXEC_NEXT_INSTRUCTION;
else
next_state=`EXEC_WRITE_ENTRY;
`normal_instruction;
`normal_instruction
end
3'b101: begin
/* Jump on (not) Parity */
@ -597,7 +587,7 @@ always @( posedge clock ) begin
next_state=`EXEC_NEXT_INSTRUCTION;
else
next_state=`EXEC_WRITE_ENTRY;
`normal_instruction;
`normal_instruction
end
3'b001: begin
/* Jump on (not) Carry */
@ -605,10 +595,10 @@ always @( posedge clock ) begin
next_state=`EXEC_NEXT_INSTRUCTION;
else
next_state=`EXEC_WRITE_ENTRY;
`normal_instruction;
`normal_instruction
end
default:begin
`invalid_instruction; /*We don't support that condition*/
`invalid_instruction /*We don't support that condition*/
end
endcase
DEPENDS_ON_PREVIOUS<=1;
@ -626,7 +616,7 @@ always @( posedge clock ) begin
OUT_MOD=3'b101;
MEM_OR_IO<=0;
next_state=`EXEC_WRITE_ENTRY;
`normal_instruction;
`normal_instruction
DEPENDS_ON_PREVIOUS<=0;
memio_address_select=0;
end
@ -711,7 +701,7 @@ always @( posedge clock ) begin
end
endcase
OUT_MOD=3'b100;/*NULL*/
`normal_instruction;
`normal_instruction
DEPENDS_ON_PREVIOUS<=0;
memio_address_select=0;
end
@ -734,7 +724,7 @@ always @( posedge clock ) begin
in_alu_sel2=2'b01;
reg_read_port2_addr<={Wbit,RM};
OUT_MOD=3'b100;/*NULL*/
`normal_instruction;
`normal_instruction
DEPENDS_ON_PREVIOUS<=0;
memio_address_select=0;
end
@ -770,7 +760,7 @@ always @( posedge clock ) begin
end
ALU_OP<=`ALU_OP_ADD;
OUT_MOD=3'b101;
`normal_instruction;
`normal_instruction
DEPENDS_ON_PREVIOUS<=0;
memio_address_select=0;
end
@ -791,7 +781,7 @@ always @( posedge clock ) begin
OUT_MOD={1'b0,INSTRUCTION[23:22]};
IN_MOD=3'b011;
RM=INSTRUCTION[18:16];
`normal_instruction;
`normal_instruction
DEPENDS_ON_PREVIOUS<=0;
memio_address_select=0;
next_state=`EXEC_WRITE_ENTRY;
@ -883,7 +873,7 @@ always @( posedge clock ) begin
OUT_MOD=IN_MOD;
DEPENDS_ON_PREVIOUS<=0;
memio_address_select=0;
`normal_instruction;
`normal_instruction
end
11'b0000_00??_???,11'b0010_10??_???,11'b0011_10??_???:begin
/* CMP - Compare Register/memory and register */
@ -929,9 +919,9 @@ always @( posedge clock ) begin
DEPENDS_ON_PREVIOUS<=0;
next_state=`EXEC_WRITE_ENTRY;
if(INSTRUCTION[25:25]==1'b0) begin
`normal_instruction;
`normal_instruction
end else begin
`unimpl_addressing_mode;
`unimpl_addressing_mode
end
end
default:begin
@ -1063,7 +1053,7 @@ module InstrSize ( input [10:0] IN, output reg [2:0] VERDICT );
end
endmodule
`ifdef INCLUDE_EARLY_CALC_CIRUIT
`ifdef INCLUDE_EARLY_CALC_CIRCUIT
module Is1 ( input [7:0] IN, output reg VERDICT );
always @* begin
casez(IN)

2
system/execute.v
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@ -304,7 +304,7 @@ always @(posedge clock) begin
else
BIU_ADDRESS_INPUT <= ALU_O;
if (write == 0) begin //TODO: don't do it that was or better yet don't do it at all somehow
if (write == 0) begin //TODO: don't do it that way or better yet don't do it at all somehow
biu_write_request <= 0;
`finished_instruction
end

2
system/fpga_config/OrangeCrab_r0.2.1/fpga_top.v
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@ -51,7 +51,7 @@ assign rgb_led0_r=rgb_led_color[0];
assign rgb_led0_g=rgb_led_color[1];
assign rgb_led0_b=rgb_led_color[2];
// A bit useless since if the cpu ERORRS out or HALTS it will continue executing anyway
// A bit useless since if the cpu ERRORS out or HALTS it will continue executing anyway
//always @(HALT or ERROR or user_button) begin
// if (HALT==1) begin
// /* yellow */

2
system/peripherals/I2C_driver.v
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@ -30,9 +30,9 @@ module I2C_driver (
reg SDA;
reg i2c_bus_dir=0;
assign SDA_=(i2c_bus_dir==0)?SDA:1'bz;
reg i2c_bus_dir=0;
reg [5:0] i2c_state = 6'b100100;
reg [3:0] data_bit_counter;

16
system/peripherals/ascii_to_HD44780_driver.v
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@ -206,17 +206,17 @@ always @(posedge clock) begin
8'd8:begin
if(next_line)begin
case(line)
2'd0: begin data<=4'h0; ; end
2'd1: begin data<=4'h4; ; end
2'd2: begin data<=4'h4; ; end
2'd3: begin data<=4'h4; ; end
2'd0: begin data<=4'h0; end
2'd1: begin data<=4'h4; end
2'd2: begin data<=4'h4; end
2'd3: begin data<=4'h4; end
endcase
end else begin
case(line)
2'd0: begin data<=4'h0; ; end
2'd1: begin data<=4'h0; ; end
2'd2: begin data<=4'h4; ; end
2'd3: begin data<=4'h4; ; end
2'd0: begin data<=4'h0; end
2'd1: begin data<=4'h0; end
2'd2: begin data<=4'h4; end
2'd3: begin data<=4'h4; end
endcase
end
if(!done_writing)begin

6
system/processor.v
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@ -37,14 +37,14 @@ module processor (
`ifdef CALCULATE_IPC
/* STATISTICS */ ,output wire new_instruction
`endif
`ifdef OTUPUT_JSON_STATISTICS
`ifdef OUTPUT_JSON_STATISTICS
/* */ ,output wire [`L1_CACHE_SIZE-1:0] L1_SIZE_STAT, output wire VALID_INSTRUCTION_STAT, output wire jump_req_debug
`endif
);
`ifdef OTUPUT_JSON_STATISTICS
`ifdef OUTPUT_JSON_STATISTICS
assign jump_req_debug=biu_jump_req;
`endif
@ -126,7 +126,7 @@ BIU BIU(
/***************** OUTPUT TO EX ****************/
/* */ ,BIU_EX_DATA_READ
`ifdef OTUPUT_JSON_STATISTICS
`ifdef OUTPUT_JSON_STATISTICS
/***************** STATISTICS *****************/
/* */ ,L1_SIZE_STAT, VALID_INSTRUCTION_STAT
`endif

18
system/system.v
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@ -28,7 +28,7 @@ module system ( input clock,input reset, output [19:0]address_bus, input [15:0]d
wire new_instruction;
`endif
`ifdef OTUPUT_JSON_STATISTICS
`ifdef OUTPUT_JSON_STATISTICS
wire unsigned [`L1_CACHE_SIZE-1:0] L1_SIZE_STAT;
wire VALID_INSTRUCTION_STAT,jump_req;
`endif
@ -44,14 +44,14 @@ processor p(
`ifdef CALCULATE_IPC
/* STATISTICS */ ,new_instruction
`endif
`ifdef OTUPUT_JSON_STATISTICS
`ifdef OUTPUT_JSON_STATISTICS
/* */ ,L1_SIZE_STAT, VALID_INSTRUCTION_STAT, jump_req
`endif
);
doublemem sysmem(address_bus,data_bus_read_,data_bus_write_,rd,wr,BHE,IOMEM);
`ifdef OTUPUT_JSON_STATISTICS
`ifdef OUTPUT_JSON_STATISTICS
string stats_name,version,commit;
integer json_file_descriptor;
`endif
@ -66,7 +66,7 @@ initial begin
$dumpfile(waveform_name);
$dumpvars(0,p,cycles);
end
`ifdef OTUPUT_JSON_STATISTICS
`ifdef OUTPUT_JSON_STATISTICS
if(!$value$plusargs("VERSION=%s",version)) version="unkown";
if(!$value$plusargs("COMMIT=%s",commit)) commit="unkown";
if($value$plusargs("STATS=%s",stats_name))begin
@ -92,7 +92,7 @@ end
// end
//end
`ifdef OTUPUT_JSON_STATISTICS
`ifdef OUTPUT_JSON_STATISTICS
reg first_json_cycle;
always @(negedge clock)begin
if(finish < 2 && json_file_descriptor!=0 && sane)begin
@ -128,7 +128,7 @@ end
`ifndef SYNTHESIS
`ifdef OTUPUT_JSON_STATISTICS
`ifdef OUTPUT_JSON_STATISTICS
reg [128:0] instruction_count_temp;
`endif
@ -165,13 +165,13 @@ end
$display("\x1b[7mInstr. per cycle : %f\x1b[m", $itor(instruction_count) / $itor(cycles) );
/* verilator lint_on REALCVT */
`endif
`ifdef OTUPUT_JSON_STATISTICS
`ifdef OUTPUT_JSON_STATISTICS
instruction_count_temp <= instruction_count;
`endif
end
2'd2: begin
finish <= 3;
`ifdef OTUPUT_JSON_STATISTICS
`ifdef OUTPUT_JSON_STATISTICS
if(json_file_descriptor!=0)
$fdisplay(json_file_descriptor,"],\n\"Total Cycles\":%0d,\n\"Instructions run\":%0d\n}",cycles-1,instruction_count_temp);
`endif
@ -208,7 +208,7 @@ end
cycles<=cycles+1;
else begin
cycles<=0;
`ifdef OTUPUT_JSON_STATISTICS
`ifdef OUTPUT_JSON_STATISTICS
instruction_count <= 0;
`endif
end

4
tools/parse_nextpnr_stats.sh
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@ -3,7 +3,7 @@ set -eu
if ! which jq &> /dev/null
then
echo to get stastics, please install jq
echo to get statistics, please install jq
exit 0
fi
@ -20,7 +20,7 @@ then
REPORT_TYPE=brief
;;
*)
echo unkown parameter "\"$1\""
echo unknown parameter "\"$1\""
exit 1
;;
esac

2
tools/plot.sh
View File

@ -5,7 +5,7 @@ print_help(){
echo "$0 <json data file> <function> <output filename>"
echo " Possible functions:"
echo " cache_time : graph of cache utilisation in bytes over time in clock cycles"
echo " cache_util_freq : graph of the likelyhood of the cache for each utilisation"
echo " cache_util_freq : graph of the likelihood of the cache for each utilisation"
}
if [ "$#" != 3 ] || ! [ -e "$1" ]