280 lines
6.3 KiB
Verilog
280 lines
6.3 KiB
Verilog
/* top.v - Implements FPGA and Board specific circuitry
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This file is part of the 9086 project.
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Copyright (c) 2023 Efthymios Kritikos
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>. */
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`include "error_header.v"
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module fpga_top(
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input clk48,
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input user_button,
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// output reset_n,
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output rgb_led0_r,
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output rgb_led0_g,
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output rgb_led0_b,
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inout gpio_0,/*sda*/
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output gpio_1 /*scl*/
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);
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wire HALT;
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wire [`ERROR_BITS-1:0]ERROR;
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wire [19:0] address_bus;
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wire [15:0] data_bus_read,data_bus_write;
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wire rd,wr,BHE,IOMEM;
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wire CPU_SPEED=counter[6];
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system system(
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/* MISC */ CPU_SPEED,reset
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/* MEMORY / IO */ ,address_bus,data_bus_read,data_bus_write,BHE,rd,wr,IOMEM,HALT,ERROR
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);
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reg [2:0]rgb_led_color;
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assign rgb_led0_r=rgb_led_color[0];
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assign rgb_led0_g=rgb_led_color[1];
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assign rgb_led0_b=rgb_led_color[2];
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// A bit useless since if the cpu ERRORS out or HALTS it will continue executing anyway
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//always @(HALT or ERROR or user_button) begin
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// if (HALT==1) begin
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// /* yellow */
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// rgb_led_color<=3'b100;
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// end else if (ERROR != `ERROR_BITS'b0) begin
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// /* red */
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// rgb_led_color<=3'b110;
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// end else begin
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// /* green */
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// rgb_led_color<=3'b101;
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// end
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//end
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// Create a 27 bit register
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reg [26:0] counter = 0;
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// Every positive edge increment register by 1
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always @(posedge clk48) begin
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counter <= counter + 1;
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end
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/*** RESET CIRCUIT ***/
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reg reset=0;
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reg [1:0] state=0;
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always @(posedge counter[15]) begin
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if(user_button==0)
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state=2'b00;
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case (state)
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2'b00:begin
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reset<=0;
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state<=2'b01;
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end
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2'b01:begin
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reset<=1;
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state<=2'b10;
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end
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default: begin
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end
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endcase
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end
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/* TODO This seems to be a bug with YOSYS. If I don't initialise the memory
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* it doesn't work (even though it does in sim), and for example if i
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* initialise 1 twice to the same value it breaks again.
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*
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* This seems to affect brainfuck_compiled.asm and specifically when the
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* compiled code starts running ( or the compiler i guess )
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*/
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initial begin
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disp_write_cache[ 0]=8'h46;
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disp_write_cache[ 1]=8'h46;
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disp_write_cache[ 2]=8'h46;
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disp_write_cache[ 3]=8'h46;
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disp_write_cache[ 4]=8'h46;
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disp_write_cache[ 5]=8'h46;
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disp_write_cache[ 6]=8'h46;
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disp_write_cache[ 7]=8'h46;
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disp_write_cache[ 8]=8'h46;
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disp_write_cache[ 9]=8'h46;
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disp_write_cache[10]=8'h46;
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disp_write_cache[11]=8'h46;
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disp_write_cache[12]=8'h46;
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disp_write_cache[13]=8'h46;
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disp_write_cache[14]=8'h46;
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disp_write_cache[15]=8'h46;
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disp_write_cache[16]=8'h46;
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disp_write_cache[17]=8'h46;
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disp_write_cache[18]=8'h46;
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disp_write_cache[19]=8'h46;
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disp_write_cache[20]=8'h46;
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disp_write_cache[21]=8'h46;
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disp_write_cache[22]=8'h46;
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disp_write_cache[23]=8'h46;
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disp_write_cache[24]=8'h46;
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disp_write_cache[25]=8'h46;
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disp_write_cache[26]=8'h46;
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disp_write_cache[27]=8'h46;
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disp_write_cache[28]=8'h46;
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disp_write_cache[29]=8'h46;
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disp_write_cache[30]=8'h46;
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disp_write_cache[31]=8'h46;
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disp_write_cache[32]=8'h46;
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disp_write_cache[33]=8'h46;
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disp_write_cache[34]=8'h46;
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disp_write_cache[35]=8'h46;
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disp_write_cache[36]=8'h46;
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disp_write_cache[37]=8'h46;
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disp_write_cache[38]=8'h46;
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disp_write_cache[39]=8'h46;
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disp_write_cache[40]=8'h46;
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disp_write_cache[41]=8'h46;
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disp_write_cache[42]=8'h46;
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disp_write_cache[43]=8'h46;
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disp_write_cache[44]=8'h46;
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disp_write_cache[45]=8'h46;
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disp_write_cache[46]=8'h46;
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disp_write_cache[47]=8'h46;
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disp_write_cache[48]=8'h46;
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disp_write_cache[49]=8'h46;
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disp_write_cache[50]=8'h46;
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disp_write_cache[51]=8'h46;
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disp_write_cache[52]=8'h46;
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disp_write_cache[53]=8'h46;
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disp_write_cache[54]=8'h46;
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disp_write_cache[55]=8'h46;
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disp_write_cache[56]=8'h46;
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disp_write_cache[57]=8'h46;
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disp_write_cache[58]=8'h46;
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disp_write_cache[59]=8'h46;
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disp_write_cache[60]=8'h46;
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disp_write_cache[61]=8'h46;
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disp_write_cache[62]=8'h46;
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disp_write_cache[63]=8'h46;
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end
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//TODO similarly as above, if I remove this the same thing breaks
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always @(negedge wr) begin
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end
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//------------------------------------------//
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// Cache to allow the slow display to have a
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// chance to keep up with the relentless CPU
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reg [5:0] disp_cache_start=0;
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reg [5:0] disp_cache_end=0;
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reg [7:0] disp_write_cache [63:0];
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reg ascii_state=0;
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always @(posedge CPU_SPEED)begin
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if(wr==0)begin
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if(IOMEM==1'b1 && address_bus[7:0]==8'hA5 )begin
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disp_write_cache[disp_cache_end]<=data_bus_write[15:8];
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disp_cache_end<=disp_cache_end+6'd1;
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end else if(IOMEM==1'b1 && address_bus[7:0]==8'hB0 )begin
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if(data_bus_write[0:0]==1)
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rgb_led_color=3'b000;
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else
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rgb_led_color=3'b111;
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end
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end else if(ascii_state==1'b0)begin
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if(ascii_data_ready&disp_cache_start!=disp_cache_end)begin
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ascii_data<=disp_write_cache[disp_cache_start];
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disp_cache_start<=disp_cache_start+6'd1;
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ascii_data_write_req<=1;
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ascii_state<=1'b1;
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end
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end
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if(ascii_state==1'b1)begin
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if(!ascii_data_ready)begin
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ascii_data_write_req<=0;
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ascii_state<=1'b0;
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end
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end
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end
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wire I2C_SPEED=counter[7];
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// Display driver
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wire ascii_data_ready;
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reg ascii_data_write_req=0;
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reg [7:0] ascii_data;
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ascii_to_HD44780_driver LCD_DRIVER(
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/* system */
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I2C_SPEED,
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1'b1,
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/* Data Input */
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ascii_data_ready,
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ascii_data_write_req,
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ascii_data,
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/* write circuitry */
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!pcf_busy,
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pcf_write_req,
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pcf_data,
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pcf_command_data
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);
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// Port expander driver
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wire pcf_write_req,pcf_command_data,pcf_busy;
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wire [3:0]pcf_data;
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wire [7:0]i2c_data;
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pcf8574_for_HD44780 PCF8574_driver(
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.clock(I2C_SPEED),
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.pcf_write_req(pcf_write_req),
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.pcf_command_data(pcf_command_data),
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.pcf_data(pcf_data),
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.pcf_busy(pcf_busy),
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.new_backlight(1'b0),
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.backlight_update(1'b0),
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.I2C_BUSY(I2C_BUSY),
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.I2C_SEND(I2C_SEND),
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.i2c_data(i2c_data)
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);
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// I2C driver
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wire SCL,SDA,I2C_BUSY,I2C_SEND;
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assign gpio_1=SCL;
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assign gpio_0=SDA;
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I2C_driver i2c_driver(
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.clock(I2C_SPEED),
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.SDA_(SDA),
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.SCL(SCL),
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.address(7'h27),
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.I2C_BUSY(I2C_BUSY),
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.I2C_SEND(I2C_SEND),
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.i2c_data(i2c_data)
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);
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endmodule
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