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Updated README, improved fpga-specific makefile options and updated the version number

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(Tim) Efthimis Kritikos 2023-11-07 14:37:22 +00:00
parent 4767a7addc
commit 1a1634c673
4 changed files with 44 additions and 15 deletions
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40
README.md
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@ -14,10 +14,15 @@ A CPU that aims to be binary compatible with the 8086 ISA, focused on optimisati
* [ ] Is Out of Order * [ ] Is Out of Order
* [ ] Is superscalar * [ ] Is superscalar
* [X] Has been successfully synthesized * [X] Has been successfully synthesized
* [ ] Has a comprehensive testing framework
### High level design overview
<img width="700" style=" margin: 10px 0px 10px 10px;" alt="9086 logo" src="readme_files/9086_overview.svg">
### Simulating it ### Simulating it
Both Verilator and Icarus Verilog can be used for simulation. You can select which one you want with the SIM variable on [common.mk](./common.mk) Both Verilator and Icarus Verilog can be used for simulation. You can select which one you want with the SIM variable on [./common.mk](./common.mk).
Specifically this list shows the software needed and the versions used during development (other versions should work as well) This list shows the software needed and the versions used during development :
* Icarus Verilog : version 12.0 OR **(preferred)** Verilator : 5.016 * Icarus Verilog : version 12.0 OR **(preferred)** Verilator : 5.016
* bin86 : 0.16.21 * bin86 : 0.16.21
@ -27,18 +32,38 @@ Specifically this list shows the software needed and the versions used during de
After that you can run `make` on the top level directory and it should build everything and start the simulation After that you can run `make` on the top level directory and it should build everything and start the simulation
### High level design overview ### Synthesis and bitstream creation ( for FPGAs )
Synthesis is based on Yosys. You need to set FPGA\_BOARD in [./common.mk](./common.mk) to the name of a directory inside [./system/fpga\_config/](system/fpga_config/). You should also check inside your board directory for config.mk for further board-specific configuration options. Then you can run `make upload` in the top level directory and it should create the bitstream and upload it.
<img width="700" style=" margin: 10px 0px 10px 10px;" alt="9086 logo" src="readme_files/9086_overview.svg"> These are the currently supported fpga boards:
### License * OrangeCrab r0.2.1
This list shows the software needed and the versions used during development :
* yosys : 0.35
* bin86 : 0.16.21
* GNU Make : 4.4.1
* xxd : 2022-01-14
* POSIX coreutils : GNU coreutils 9.4
Additionally, for ECP5 FPGAs:
* prjtrellis : 1.4 ( database commit 4dda149b9e4f1753ebc8b011ece2fe794be1281a )
* nextpnr : 0.6
Additionally, for FPGAs using the [foboot](https://github.com/im-tomu/foboot) bootloader
* dfu-util : 0.11
### License and Copyright
All parts of this project and files in this repository are licensed under the GNU General Public License version 3 or later All parts of this project and files in this repository are licensed under the GNU General Public License version 3 or later
Efthymios Kritikos is the copyright owner for all files except the following: Efthymios Kritikos is the copyright owner for all files except the following:
| File | Copyright owner | Original license | | File | Copyright owner | Original license |
| :-----------------------------------------------------: | :-------------: | :--------------: | | :--------------------------------------------------------: | :-------------: | :--------------: |
| system/fpga_config/OrangeCrab_r0.2.1/pin_constraint.pcf | Greg Davill | MIT | | system/fpga\_config/OrangeCrab\_r0.2.1/pin\_constraint.pcf | Greg Davill | MIT |
### Version names ### Version names
The version name consist of three numbers: The version name consist of three numbers:
@ -48,3 +73,4 @@ The version name consist of three numbers:
1. Patch level 1. Patch level
For example v1.3.2 aims to support 80186 code, is on the fourth milestone and has 2 bug fixes since the milestone was reached. For example v1.3.2 aims to support 80186 code, is on the fourth milestone and has 2 bug fixes since the milestone was reached.
A "-dev" suffix denotes that the code is in the process to become that version, so in-between that and the previous.

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common.mk
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@ -20,14 +20,8 @@ FPGA_BOARD=OrangeCrab_r0.2.1
# BOARD: the options are the directories in system/fpga_config/. # BOARD: the options are the directories in system/fpga_config/.
# Select the one you have # Select the one you have
#### ECP5 specific #### VERSION="v0.3.0-dev"
ECP5_DEVICE=25F
# ECP5_DEVICE: 25F: Create bitstream for the LFE5U-25F
# 85F: Create bitstream for the LFE5U-85F
ECP5_PACKAGE=CSFBGA285
# ECP5_PACKAGE: CSFBGA285: The one used in OrangeCrab
VERSION="v0.2.0"
COMMIT=$(shell git log --pretty=format:'%H' -1 |cat) COMMIT=$(shell git log --pretty=format:'%H' -1 |cat)
ifeq "${QUIET}" "1" ifeq "${QUIET}" "1"

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system/Makefile
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@ -55,6 +55,8 @@ ${VERILATOR_BIN}.mk: ${VERILATOR_TESTBENCH} ${TOP_LEVEL_SOURCE} ${SOURCES} ${INC
${QUIET_VERILATOR} ${QUIET_VERILATOR}
${Q}verilator -DBUILTIN_RAM=32768 -UNOT_FULL -DCALCULATE_IPC -DOTUPUT_JSON_STATISTICS ${VERILATOR_OPTS} $^ ${Q}verilator -DBUILTIN_RAM=32768 -UNOT_FULL -DCALCULATE_IPC -DOTUPUT_JSON_STATISTICS ${VERILATOR_OPTS} $^
include fpga_config/${FPGA_BOARD}/config.mk
# Synthesis and bitstream creation for ECP5 # Synthesis and bitstream creation for ECP5
ifeq "${ECP5_DEVICE}" "25F" ifeq "${ECP5_DEVICE}" "25F"
NEXTPNR_ECP5_DEV=--25k NEXTPNR_ECP5_DEV=--25k

7
system/fpga_config/OrangeCrab_r0.2.1/config.mk Normal file
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@ -0,0 +1,7 @@
#### ECP5 specific ####
ECP5_DEVICE=25F
# ECP5_DEVICE: 25F: Create bitstream for the LFE5U-25F
# 85F: Create bitstream for the LFE5U-85F
ECP5_PACKAGE=CSFBGA285
# ECP5_PACKAGE: CSFBGA285: The one used in OrangeCrab