Added config file (mainly for debug verbosity) and kind of patched some weird behaviour when clock is stopped
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@ -1,5 +1,5 @@
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SOURCES=processor.v testbench.v memory.v registers.v alu.v
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SOURCES=processor.v testbench.v memory.v registers.v alu.v
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INCLUDES=proc_state_def.v
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INCLUDES=proc_state_def.v alu_header.v config.v
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VVP=processor.vvp
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VVP=processor.vvp
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.PHONY: brainf
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.PHONY: brainf
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3
cpu/config.v
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3
cpu/config.v
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//Runtime Verbosity
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`define DEBUG_REG_WRITES
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`define DEBUG_PC_ADDRESS
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`include "proc_state_def.v"
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`include "proc_state_def.v"
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`include "alu_header.v"
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`include "alu_header.v"
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`include "config.v"
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module mux4 (in1,in2,in3,in4, sel,out);
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module mux4 (in1,in2,in3,in4, sel,out);
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input [0:1] sel;
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input [0:1] sel;
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@ -72,6 +73,7 @@ always @(negedge reset) begin
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@(negedge clock);
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@(negedge clock);
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state=`PROC_IF_STATE_ENTRY;
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state=`PROC_IF_STATE_ENTRY;
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IN_MOD=2'b11;
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IN_MOD=2'b11;
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ERROR=0;
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end
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end
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end
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end
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@ -168,8 +170,14 @@ always @(posedge clock) begin
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`PROC_HALT_STATE:begin
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`PROC_HALT_STATE:begin
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end
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end
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`PROC_IF_STATE_ENTRY:begin
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`PROC_IF_STATE_ENTRY:begin
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ERROR=0;
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`ifdef DEBUG_PC_ADDRESS
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$display("Fetched instruction at %04x",{ProgCount[18:0],unaligned_access});
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/* Weird (possible bug) where even though the
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* testbench stop the clock after ERROR gets
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* raised the logic for the rising edge still
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* gets triggered printing this debug message. */
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if(ERROR!=1)
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$display("Fetched instruction at %04x",{ProgCount[18:0],unaligned_access});
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`endif
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external_address_bus <= ProgCount;
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external_address_bus <= ProgCount;
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read <= 0;
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read <= 0;
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write <= 1;
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write <= 1;
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@ -565,7 +573,6 @@ always @(posedge clock) begin
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reg_write_data=ALU_1O;
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reg_write_data=ALU_1O;
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FLAGS[7:0] = ALU_FLAGS[7:0];
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FLAGS[7:0] = ALU_FLAGS[7:0];
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state=`PROC_EX_STATE_EXIT;
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state=`PROC_EX_STATE_EXIT;
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ERROR=0;
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end
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end
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endcase
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endcase
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end
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end
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@ -1,3 +1,4 @@
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`include "config.v"
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/* Register address fromat:
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/* Register address fromat:
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* [W-bit] [ 3-bit address] */
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* [W-bit] [ 3-bit address] */
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@ -14,8 +15,6 @@ assign read_port1_data = !read_port1_oe ?
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( read_port1_addr[3:3] ? registers[read_port1_addr[2:0]] :
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( read_port1_addr[3:3] ? registers[read_port1_addr[2:0]] :
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( read_port1_addr[2:2] ? {8'b0,registers[read_port1_addr[2:0]][15:8]} : {8'b0,registers[read_port1_addr[2:0]][7:0]} ) ) : 'hz;
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( read_port1_addr[2:2] ? {8'b0,registers[read_port1_addr[2:0]][15:8]} : {8'b0,registers[read_port1_addr[2:0]][7:0]} ) ) : 'hz;
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`define DEBUG_REG_WRITES
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`ifdef DEBUG_REG_WRITES
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`ifdef DEBUG_REG_WRITES
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string debug_name;
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string debug_name;
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`endif
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`endif
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@ -21,7 +21,7 @@ integer cycles=0;
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initial begin
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initial begin
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$dumpfile("test.lx2");
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$dumpfile("test.lx2");
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$dumpvars(0,p);
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$dumpvars(0,p,u1);
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reset = 0;
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reset = 0;
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clk_enable <= 1;
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clk_enable <= 1;
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@ -38,6 +38,7 @@ always @(posedge HALT) begin
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end
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end
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always @(posedge ERROR) begin
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always @(posedge ERROR) begin
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clk_enable <= 0;
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$display("PROCESSOR RUN INTO AN ERROR.\nCycles run for: %d",cycles);
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$display("PROCESSOR RUN INTO AN ERROR.\nCycles run for: %d",cycles);
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$writememh("memdump.txt", bootrom.memory);
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$writememh("memdump.txt", bootrom.memory);
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#(`CPU_SPEED) //Just for the waveform
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#(`CPU_SPEED) //Just for the waveform
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