From 0d4221f9deabc0d66eb141dc9a6968eb5bcf8920 Mon Sep 17 00:00:00 2001
From: "(Tim) Efthimis Kritikos" <efkf@firemail.cc>
Date: Mon, 13 Feb 2023 15:24:21 +0000
Subject: [PATCH] Added config file (mainly for debug verbosity) and kind of
 patched some weird behaviour when clock is stopped

---
 cpu/Makefile    |  2 +-
 cpu/config.v    |  3 +++
 cpu/processor.v | 13 ++++++++++---
 cpu/registers.v |  3 +--
 cpu/testbench.v |  3 ++-
 5 files changed, 17 insertions(+), 7 deletions(-)
 create mode 100644 cpu/config.v

diff --git a/cpu/Makefile b/cpu/Makefile
index f980d99..c48954e 100644
--- a/cpu/Makefile
+++ b/cpu/Makefile
@@ -1,5 +1,5 @@
 SOURCES=processor.v testbench.v memory.v registers.v alu.v
-INCLUDES=proc_state_def.v
+INCLUDES=proc_state_def.v alu_header.v config.v
 VVP=processor.vvp
 
 .PHONY: brainf
diff --git a/cpu/config.v b/cpu/config.v
new file mode 100644
index 0000000..cece0f2
--- /dev/null
+++ b/cpu/config.v
@@ -0,0 +1,3 @@
+//Runtime Verbosity
+`define DEBUG_REG_WRITES
+`define DEBUG_PC_ADDRESS
diff --git a/cpu/processor.v b/cpu/processor.v
index 899e8dc..e9aaf40 100644
--- a/cpu/processor.v
+++ b/cpu/processor.v
@@ -1,5 +1,6 @@
 `include "proc_state_def.v"
 `include "alu_header.v"
+`include "config.v"
 
 module mux4 (in1,in2,in3,in4, sel,out); 
 input [0:1] sel;
@@ -72,6 +73,7 @@ always @(negedge reset) begin
 		@(negedge clock);
 		state=`PROC_IF_STATE_ENTRY;
 		IN_MOD=2'b11;
+		ERROR=0;
 	end
 end
 
@@ -168,8 +170,14 @@ always @(posedge clock) begin
 		`PROC_HALT_STATE:begin
 		end
 		`PROC_IF_STATE_ENTRY:begin
-			ERROR=0;
-			$display("Fetched instruction at %04x",{ProgCount[18:0],unaligned_access});
+			`ifdef DEBUG_PC_ADDRESS
+				/* Weird (possible bug) where even though the
+				* testbench stop the clock after ERROR gets
+				* raised the logic for the rising edge still
+				* gets triggered printing this debug message. */
+				if(ERROR!=1)
+					$display("Fetched instruction at %04x",{ProgCount[18:0],unaligned_access});
+			`endif
 			external_address_bus <= ProgCount;
 			read <= 0;
 			write <= 1;
@@ -565,7 +573,6 @@ always @(posedge clock) begin
 			reg_write_data=ALU_1O;
 			FLAGS[7:0] = ALU_FLAGS[7:0];
 			state=`PROC_EX_STATE_EXIT;
-			ERROR=0;
 		end
 	endcase
 end
diff --git a/cpu/registers.v b/cpu/registers.v
index e004c04..485e02e 100644
--- a/cpu/registers.v
+++ b/cpu/registers.v
@@ -1,3 +1,4 @@
+`include "config.v"
 
 /* Register address fromat:
 * [W-bit] [ 3-bit address] */
@@ -14,8 +15,6 @@ assign read_port1_data = !read_port1_oe ?
 	( read_port1_addr[3:3] ? registers[read_port1_addr[2:0]] :
 	( read_port1_addr[2:2] ? {8'b0,registers[read_port1_addr[2:0]][15:8]} : {8'b0,registers[read_port1_addr[2:0]][7:0]} ) ) : 'hz;
 
-`define DEBUG_REG_WRITES
-
 `ifdef DEBUG_REG_WRITES
 	string debug_name;
 `endif
diff --git a/cpu/testbench.v b/cpu/testbench.v
index 19019ff..ec59a69 100644
--- a/cpu/testbench.v
+++ b/cpu/testbench.v
@@ -21,7 +21,7 @@ integer cycles=0;
 
 initial begin
 	$dumpfile("test.lx2");
-	$dumpvars(0,p);
+	$dumpvars(0,p,u1);
 	reset = 0;
 	clk_enable <= 1;
 
@@ -38,6 +38,7 @@ always @(posedge HALT) begin
 end
 
 always @(posedge ERROR) begin
+	clk_enable <= 0;
 	$display("PROCESSOR RUN INTO AN ERROR.\nCycles run for: %d",cycles);
 	$writememh("memdump.txt", bootrom.memory);
 	#(`CPU_SPEED) //Just for the waveform