Added config file (mainly for debug verbosity) and kind of patched some weird behaviour when clock is stopped

This commit is contained in:
(Tim) Efthimis Kritikos 2023-02-13 15:24:21 +00:00
parent 16e02e0788
commit 0d4221f9de
5 changed files with 17 additions and 7 deletions

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@ -1,5 +1,5 @@
SOURCES=processor.v testbench.v memory.v registers.v alu.v SOURCES=processor.v testbench.v memory.v registers.v alu.v
INCLUDES=proc_state_def.v INCLUDES=proc_state_def.v alu_header.v config.v
VVP=processor.vvp VVP=processor.vvp
.PHONY: brainf .PHONY: brainf

3
cpu/config.v Normal file
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@ -0,0 +1,3 @@
//Runtime Verbosity
`define DEBUG_REG_WRITES
`define DEBUG_PC_ADDRESS

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@ -1,5 +1,6 @@
`include "proc_state_def.v" `include "proc_state_def.v"
`include "alu_header.v" `include "alu_header.v"
`include "config.v"
module mux4 (in1,in2,in3,in4, sel,out); module mux4 (in1,in2,in3,in4, sel,out);
input [0:1] sel; input [0:1] sel;
@ -72,6 +73,7 @@ always @(negedge reset) begin
@(negedge clock); @(negedge clock);
state=`PROC_IF_STATE_ENTRY; state=`PROC_IF_STATE_ENTRY;
IN_MOD=2'b11; IN_MOD=2'b11;
ERROR=0;
end end
end end
@ -168,8 +170,14 @@ always @(posedge clock) begin
`PROC_HALT_STATE:begin `PROC_HALT_STATE:begin
end end
`PROC_IF_STATE_ENTRY:begin `PROC_IF_STATE_ENTRY:begin
ERROR=0; `ifdef DEBUG_PC_ADDRESS
/* Weird (possible bug) where even though the
* testbench stop the clock after ERROR gets
* raised the logic for the rising edge still
* gets triggered printing this debug message. */
if(ERROR!=1)
$display("Fetched instruction at %04x",{ProgCount[18:0],unaligned_access}); $display("Fetched instruction at %04x",{ProgCount[18:0],unaligned_access});
`endif
external_address_bus <= ProgCount; external_address_bus <= ProgCount;
read <= 0; read <= 0;
write <= 1; write <= 1;
@ -565,7 +573,6 @@ always @(posedge clock) begin
reg_write_data=ALU_1O; reg_write_data=ALU_1O;
FLAGS[7:0] = ALU_FLAGS[7:0]; FLAGS[7:0] = ALU_FLAGS[7:0];
state=`PROC_EX_STATE_EXIT; state=`PROC_EX_STATE_EXIT;
ERROR=0;
end end
endcase endcase
end end

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@ -1,3 +1,4 @@
`include "config.v"
/* Register address fromat: /* Register address fromat:
* [W-bit] [ 3-bit address] */ * [W-bit] [ 3-bit address] */
@ -14,8 +15,6 @@ assign read_port1_data = !read_port1_oe ?
( read_port1_addr[3:3] ? registers[read_port1_addr[2:0]] : ( read_port1_addr[3:3] ? registers[read_port1_addr[2:0]] :
( read_port1_addr[2:2] ? {8'b0,registers[read_port1_addr[2:0]][15:8]} : {8'b0,registers[read_port1_addr[2:0]][7:0]} ) ) : 'hz; ( read_port1_addr[2:2] ? {8'b0,registers[read_port1_addr[2:0]][15:8]} : {8'b0,registers[read_port1_addr[2:0]][7:0]} ) ) : 'hz;
`define DEBUG_REG_WRITES
`ifdef DEBUG_REG_WRITES `ifdef DEBUG_REG_WRITES
string debug_name; string debug_name;
`endif `endif

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@ -21,7 +21,7 @@ integer cycles=0;
initial begin initial begin
$dumpfile("test.lx2"); $dumpfile("test.lx2");
$dumpvars(0,p); $dumpvars(0,p,u1);
reset = 0; reset = 0;
clk_enable <= 1; clk_enable <= 1;
@ -38,6 +38,7 @@ always @(posedge HALT) begin
end end
always @(posedge ERROR) begin always @(posedge ERROR) begin
clk_enable <= 0;
$display("PROCESSOR RUN INTO AN ERROR.\nCycles run for: %d",cycles); $display("PROCESSOR RUN INTO AN ERROR.\nCycles run for: %d",cycles);
$writememh("memdump.txt", bootrom.memory); $writememh("memdump.txt", bootrom.memory);
#(`CPU_SPEED) //Just for the waveform #(`CPU_SPEED) //Just for the waveform