Improved parallelism
This commit is contained in:
parent
fe0426a77b
commit
00aa828ddc
@ -1,15 +1,15 @@
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[*]
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[*] GTKWave Analyzer v3.3.111 (w)1999-2020 BSI
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[*] Sat May 13 03:32:49 2023
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[*] Sat May 13 08:57:35 2023
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[*]
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[dumpfile] "/home/user/9086_take_two/system/boot_code.fst"
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[dumpfile_mtime] "Sat May 13 03:30:49 2023"
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[dumpfile_size] 8561
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[savefile] "/home/user/9086_take_two/gtkwave_savefile.gtkw"
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[timestart] 102870000000
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[dumpfile] "/home/user/9086/system/boot_code.fst"
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[dumpfile_mtime] "Sat May 13 08:57:31 2023"
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[dumpfile_size] 13788
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[savefile] "/home/user/9086/gtkwave_savefile.gtkw"
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[timestart] 87160000000
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[size] 1140 993
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[pos] -1 -1
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*-33.395050 121840000000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
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*-31.895050 93500000000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
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[treeopen] TOP.
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[treeopen] TOP.system.
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[treeopen] TOP.system.p.
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@ -20,42 +20,40 @@
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[signals_width] 231
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[sst_expanded] 1
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[sst_vpaned_height] 296
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@28
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@29
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TOP.system.clock
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TOP.system.reset
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@22
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@23
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TOP.system.address_bus[19:0]
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TOP.system.data_bus[15:0]
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@28
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@29
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TOP.system.p.read
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TOP.system.p.write
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@200
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@201
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-
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@28
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@29
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TOP.system.p.BIU.VALID_INSTRUCTION
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TOP.system.p.valid_exec_data
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@22
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@23
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TOP.system.p.execute_unit.INSTRUCTION_BUFFER[23:0]
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TOP.system.p.BIU.biu_state[3:0]
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@28
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TOP.system.p.execute_unit.exec_state[3:0]
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TOP.system.p.BIU.write_request
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@29
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TOP.system.p.execute_unit.exec_state[3:0]
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TOP.system.p.execute_unit.work
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TOP.system.p.BIU.write_request
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TOP.system.p.BIU.read_request
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@28
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TOP.system.p.SIMPLE_MICRO
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@22
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@23
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TOP.system.p.ucode_seq_addr[4:0]
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@28
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@29
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TOP.system.p.execute_unit.biu_jump_req
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TOP.system.p.execute_unit.stall
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@200
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@201
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-
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@28
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@29
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TOP.system.p.ERROR[2:0]
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TOP.system.IOMEM
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TOP.system.p.HALT
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@22
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@23
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TOP.system.p.BIU.INSTRUCTION[31:0]
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TOP.system.p.decoder.seq_addr_entry[4:0]
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TOP.system.p.BIU.FIFO_end[3:0]
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40
system/biu.v
40
system/biu.v
@ -42,7 +42,7 @@ module BIU (
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/* */ inout [15:0] external_data_bus,output reg read, output reg write,output reg BHE,output reg IOMEM,
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/* Internal */ output reg [31:0] INSTRUCTION, output reg VALID_INSTRUCTION, output reg [15:0] INSTRUCTION_LOCATION, input jump_req,
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/* */ input[15:0] ADDRESS_INPUT, inout [15:0] DATA, input write_request, input read_request, input Wbit, output reg VALID_DATA, input MEM_OR_IO,
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/* */ input [`PROC_STATE_BITS-1:0] proc_state, input SIMPLE_MICRO,input stall
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/* */ input [`PROC_STATE_BITS-1:0] proc_state, input SIMPLE_MICRO
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);
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reg [15:0] data_bus_output_register;
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@ -121,26 +121,24 @@ always @(posedge clock) begin
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end
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end
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if ( !stall ) begin
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if((Isit1==1) && (FIFO_SIZE!=0) && `EARLY_VALID_INSTRUCTION_)begin
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VALID_INSTRUCTION <= 1;
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INSTRUCTION[31:24] <= INPUT_FIFO[FIFO_start];
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end else if((fifoIsize==2) && (FIFO_SIZE > 1) && `EARLY_VALID_INSTRUCTION_)begin
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VALID_INSTRUCTION <= 1;
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INSTRUCTION[31:24] <= INPUT_FIFO[FIFO_start];
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INSTRUCTION[23:16] <= INPUT_FIFO[FIFO_start+4'd1];
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end else if((fifoIsize==3) && (FIFO_SIZE > 2) && `EARLY_VALID_INSTRUCTION_)begin
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VALID_INSTRUCTION <= 1;
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INSTRUCTION[31:24] <= INPUT_FIFO[FIFO_start];
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INSTRUCTION[23:16] <= INPUT_FIFO[FIFO_start+4'd1];
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INSTRUCTION[15: 8] <= INPUT_FIFO[FIFO_start+4'd2];
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end else if(FIFO_SIZE>3)begin
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VALID_INSTRUCTION <= 1;
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INSTRUCTION[31:24] <= INPUT_FIFO[FIFO_start];
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INSTRUCTION[23:16] <= INPUT_FIFO[FIFO_start+4'd1];
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INSTRUCTION[15: 8] <= INPUT_FIFO[FIFO_start+4'd2];
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INSTRUCTION[ 7: 0] <= INPUT_FIFO[FIFO_start+4'd3];
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end
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if((Isit1==1) && (FIFO_SIZE!=0) && `EARLY_VALID_INSTRUCTION_)begin
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VALID_INSTRUCTION <= 1;
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INSTRUCTION[31:24] <= INPUT_FIFO[FIFO_start];
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end else if((fifoIsize==2) && (FIFO_SIZE > 1) && `EARLY_VALID_INSTRUCTION_)begin
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VALID_INSTRUCTION <= 1;
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INSTRUCTION[31:24] <= INPUT_FIFO[FIFO_start];
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INSTRUCTION[23:16] <= INPUT_FIFO[FIFO_start+4'd1];
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end else if((fifoIsize==3) && (FIFO_SIZE > 2) && `EARLY_VALID_INSTRUCTION_)begin
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VALID_INSTRUCTION <= 1;
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INSTRUCTION[31:24] <= INPUT_FIFO[FIFO_start];
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INSTRUCTION[23:16] <= INPUT_FIFO[FIFO_start+4'd1];
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INSTRUCTION[15: 8] <= INPUT_FIFO[FIFO_start+4'd2];
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end else if(FIFO_SIZE>3)begin
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VALID_INSTRUCTION <= 1;
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INSTRUCTION[31:24] <= INPUT_FIFO[FIFO_start];
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INSTRUCTION[23:16] <= INPUT_FIFO[FIFO_start+4'd1];
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INSTRUCTION[15: 8] <= INPUT_FIFO[FIFO_start+4'd2];
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INSTRUCTION[ 7: 0] <= INPUT_FIFO[FIFO_start+4'd3];
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end
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end
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@ -20,7 +20,7 @@
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module execute_unit (
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/* GENERAL */ input clock, input reset ,input Wbit, input Sbit, input opcode_size,input [23:0] INSTRUCTION_BUFFER,input valid_input
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/* */ ,input [2:0] IN_MOD, input [2:0] OUT_MOD, input memio_address_select, input [15:0] ProgCount, input [2:0] RM, output reg [`ERROR_BITS-1:0] ERROR , input write /*TODO: REMOVE!!*/
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/* */ ,input set_initial_values,output stall
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/* */ ,input set_initial_values, output reg work
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/* PARAM */ ,input [15:0] PARAM1_INIT, input [15:0] PARAM2_INIT
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/* STATE CONTROL */ ,output [`EXEC_STATE_BITS-1:0] _exec_state_, input [`EXEC_STATE_BITS-1:0] init_state
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/* ALU CONTROL */ ,input [1:0] in_alu_sel1, input [1:0] in_alu_sel2, input [`ALU_OP_BITS-1:0] ALU_OP, output [15:0] _ALU_O_
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@ -29,8 +29,6 @@ module execute_unit (
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/* BIU */ ,output reg [15:0] BIU_ADDRESS_INPUT,output reg biu_write_request, output reg biu_read_request, input BIU_VALID_DATA, input [15:0] BIU_DATA, output reg biu_data_direction, output reg biu_jump_req
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);
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assign stall = work&valid_input;
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assign _exec_state_ = exec_state;
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assign _ALU_O_ = ALU_O;
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@ -75,6 +73,9 @@ always @(posedge valid_input) begin
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if(work == 0)begin
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exec_state <= init_state;
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work <= 1;
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reg_write_we <= 1;
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biu_jump_req <= 0;
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use_exec_reg_addr <= 0;
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end
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end
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@ -93,7 +94,6 @@ end
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`define unimpl_addressing_mode exec_state <= `EXEC_DONE;ERROR <= `ERR_UNIMPL_ADDRESSING_MODE;
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reg work;
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always @(posedge clock) begin
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case (exec_state)
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`EXEC_RESET: begin
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@ -107,10 +107,14 @@ always @(posedge clock) begin
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ERROR <= `ERR_NO_ERROR;
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end
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`EXEC_DONE:begin
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work <= 0;
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reg_write_we <= 1;
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biu_jump_req <= 0;
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use_exec_reg_addr <= 0;
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if(valid_input)begin
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exec_state <= init_state;
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work <= 1;
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end else
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work <= 0;
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end
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`EXEC_DE_LOAD_REG_TO_PARAM:begin
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work <= 1;
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@ -240,12 +244,11 @@ always @(posedge clock) begin
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end
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end
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`EXEC_NEXT_INSTRUCTION:begin
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work <= 1;
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work <= 0;
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/*necessary for biu to see we went on another state from decode to give us a new instruction*/
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exec_state <= `EXEC_DONE;
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end
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`EXEC_WRITE_ENTRY:begin
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work <= 1;
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FLAGS[7:0] <= ALU_FLAGS[7:0];
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case(OUT_MOD)
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3'b000,
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@ -294,35 +297,41 @@ always @(posedge clock) begin
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exec_state <= `EXEC_MEMIO_WRITE;
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end
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endcase
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work <= 1;
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end
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3'b011:begin
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reg_write_we <= 0;
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exec_state <= `EXEC_DONE;
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work <= 0;
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end
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3'b100:begin /*No output*/
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exec_state <= `EXEC_DONE;
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work <= 0;
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end
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3'b101:begin /* Program Counter*/
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BIU_ADDRESS_INPUT <= ALU_O[15:0];
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biu_jump_req <= 1;
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exec_state <= `EXEC_DONE;
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work <= 0;
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end
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3'b110:begin /* SP Indirect write*/
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reg_read_port1_addr <= 4'b1100;
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use_exec_reg_addr <= 1;
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exec_state <= `EXEC_MEMIO_WRITE;
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work <= 1;
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end
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3'b111:begin /* Write to PRAM1 (for microcode calculations) */
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PARAM1 <= ALU_O;
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exec_state <= `EXEC_DONE;
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work <= 0;
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end
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default:begin
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`unimpl_addressing_mode
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work <= 1;
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end
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endcase
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end
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`EXEC_MEMIO_WRITE:begin
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work <= 1;
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/* if memio_address_select == 0 ADDRESS: reg_read_port1_data DATA:ALU1_O */
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/* if memio_address_select == 1 ADDRESS: ALU1_O DATA: reg_read_port1_data */
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@ -336,7 +345,9 @@ always @(posedge clock) begin
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if (write == 0) begin //TODO: don't do it that was or better yet don't do it at all somehow
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biu_write_request <= 0;
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exec_state <= `EXEC_DONE;
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end
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work <= 0;
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end else
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work <= 1;
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end
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`EXEC_HALT:begin
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@ -72,11 +72,11 @@ assign OUT_MOD=DE_OUTPUT_sampled[49:47];
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wire [`ALU_OP_BITS-1:0] ALU_OP;
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assign ALU_OP = DE_OUTPUT_sampled[42:40];
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wire stall;
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wire work;
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execute_unit execute_unit (
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/* GENERAL */ clock, reset, Wbit, Sbit, opcode_size, INSTRUCTION_BUFFER,valid_exec_data
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/* */ ,IN_MOD, OUT_MOD,memio_address_select, ProgCount, RM, EXEC_ERROR, write
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/* */ ,set_initial_values,stall
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/* */ ,set_initial_values,work
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/* PARAM */ ,PARAM1_INIT,PARAM2_INIT
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/* STATE CONTROL */ ,exec_state, next_state
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/* ALU CONTROL */ ,in_alu_sel1, in_alu_sel2, ALU_OP, ALU_O
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@ -98,7 +98,7 @@ BIU BIU(
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/* */ ,external_data_bus,read,write,BHE,IOMEM
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/* Internal */ ,INSTRUCTION,VALID_INSTRUCTION,INSTRUCTION_LOCATION,biu_jump_req
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/* */ ,BIU_ADDRESS_INPUT,BIU_DATA,biu_write_request,biu_read_request,Wbit,BIU_VALID_DATA,MEM_OR_IO
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/* */ ,state,SIMPLE_MICRO,stall
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/* */ ,state,SIMPLE_MICRO
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);
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assign BIU_DATA= biu_data_direction ? 16'hz : (memio_address_select ? reg_read_port1_data : ALU_O);
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@ -195,8 +195,8 @@ always @(posedge clock) begin
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state <= `PROC_DE_STATE_ENTRY;
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end
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`PROC_DE_STATE_ENTRY:begin
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if (!stall) begin
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if(VALID_INSTRUCTION==1) begin
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if(VALID_INSTRUCTION==1) begin
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if(work==0) begin
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DE_OUTPUT_sampled <= DE_OUTPUT;
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if(SIMPLE_MICRO==0)begin
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@ -221,16 +221,14 @@ always @(posedge clock) begin
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end
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end
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`PROC_WAIT:begin
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if(!stall) begin
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set_initial_values<=1;
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valid_exec_data<=0;
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state <= `PROC_DE_STATE_ENTRY;
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if( SIMPLE_MICRO == 1 ) begin
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ucode_seq_addr <= ucode_seq_addr_entry; /*Reused for next address*/
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if( ucode_seq_addr_entry == `UCODE_NO_INSTRUCTION )begin
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/*Finished microcode*/
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SIMPLE_MICRO <= 0;
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end
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set_initial_values<=1;
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valid_exec_data<=0;
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state <= `PROC_DE_STATE_ENTRY;
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if( SIMPLE_MICRO == 1 ) begin
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ucode_seq_addr <= ucode_seq_addr_entry; /*Reused for next address*/
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if( ucode_seq_addr_entry == `UCODE_NO_INSTRUCTION )begin
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/*Finished microcode*/
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SIMPLE_MICRO <= 0;
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end
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end
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end
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