From 00aa828ddca807449e1bb0e6d3b35a4c7b9bfd13 Mon Sep 17 00:00:00 2001 From: "(Tim) Efthimis Kritikos" Date: Sat, 13 May 2023 10:52:44 +0100 Subject: [PATCH] Improved parallelism --- gtkwave_savefile.gtkw | 44 +++++++++++++++++++++---------------------- system/biu.v | 40 +++++++++++++++++++-------------------- system/execute.v | 29 +++++++++++++++++++--------- system/processor.v | 28 +++++++++++++-------------- 4 files changed, 73 insertions(+), 68 deletions(-) diff --git a/gtkwave_savefile.gtkw b/gtkwave_savefile.gtkw index da2c35d..ee3cd41 100644 --- a/gtkwave_savefile.gtkw +++ b/gtkwave_savefile.gtkw @@ -1,15 +1,15 @@ [*] [*] GTKWave Analyzer v3.3.111 (w)1999-2020 BSI -[*] Sat May 13 03:32:49 2023 +[*] Sat May 13 08:57:35 2023 [*] -[dumpfile] "/home/user/9086_take_two/system/boot_code.fst" -[dumpfile_mtime] "Sat May 13 03:30:49 2023" -[dumpfile_size] 8561 -[savefile] "/home/user/9086_take_two/gtkwave_savefile.gtkw" -[timestart] 102870000000 +[dumpfile] "/home/user/9086/system/boot_code.fst" +[dumpfile_mtime] "Sat May 13 08:57:31 2023" +[dumpfile_size] 13788 +[savefile] "/home/user/9086/gtkwave_savefile.gtkw" +[timestart] 87160000000 [size] 1140 993 [pos] -1 -1 -*-33.395050 121840000000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +*-31.895050 93500000000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 [treeopen] TOP. [treeopen] TOP.system. [treeopen] TOP.system.p. @@ -20,42 +20,40 @@ [signals_width] 231 [sst_expanded] 1 [sst_vpaned_height] 296 -@28 +@29 TOP.system.clock TOP.system.reset -@22 +@23 TOP.system.address_bus[19:0] TOP.system.data_bus[15:0] -@28 +@29 TOP.system.p.read TOP.system.p.write -@200 +@201 - -@28 +@29 TOP.system.p.BIU.VALID_INSTRUCTION TOP.system.p.valid_exec_data -@22 +@23 TOP.system.p.execute_unit.INSTRUCTION_BUFFER[23:0] TOP.system.p.BIU.biu_state[3:0] -@28 -TOP.system.p.execute_unit.exec_state[3:0] -TOP.system.p.BIU.write_request @29 +TOP.system.p.execute_unit.exec_state[3:0] +TOP.system.p.execute_unit.work +TOP.system.p.BIU.write_request TOP.system.p.BIU.read_request -@28 TOP.system.p.SIMPLE_MICRO -@22 +@23 TOP.system.p.ucode_seq_addr[4:0] -@28 +@29 TOP.system.p.execute_unit.biu_jump_req -TOP.system.p.execute_unit.stall -@200 +@201 - -@28 +@29 TOP.system.p.ERROR[2:0] TOP.system.IOMEM TOP.system.p.HALT -@22 +@23 TOP.system.p.BIU.INSTRUCTION[31:0] TOP.system.p.decoder.seq_addr_entry[4:0] TOP.system.p.BIU.FIFO_end[3:0] diff --git a/system/biu.v b/system/biu.v index beb0a5a..50fec42 100644 --- a/system/biu.v +++ b/system/biu.v @@ -42,7 +42,7 @@ module BIU ( /* */ inout [15:0] external_data_bus,output reg read, output reg write,output reg BHE,output reg IOMEM, /* Internal */ output reg [31:0] INSTRUCTION, output reg VALID_INSTRUCTION, output reg [15:0] INSTRUCTION_LOCATION, input jump_req, /* */ input[15:0] ADDRESS_INPUT, inout [15:0] DATA, input write_request, input read_request, input Wbit, output reg VALID_DATA, input MEM_OR_IO, -/* */ input [`PROC_STATE_BITS-1:0] proc_state, input SIMPLE_MICRO,input stall +/* */ input [`PROC_STATE_BITS-1:0] proc_state, input SIMPLE_MICRO ); reg [15:0] data_bus_output_register; @@ -121,26 +121,24 @@ always @(posedge clock) begin end end - if ( !stall ) begin - if((Isit1==1) && (FIFO_SIZE!=0) && `EARLY_VALID_INSTRUCTION_)begin - VALID_INSTRUCTION <= 1; - INSTRUCTION[31:24] <= INPUT_FIFO[FIFO_start]; - end else if((fifoIsize==2) && (FIFO_SIZE > 1) && `EARLY_VALID_INSTRUCTION_)begin - VALID_INSTRUCTION <= 1; - INSTRUCTION[31:24] <= INPUT_FIFO[FIFO_start]; - INSTRUCTION[23:16] <= INPUT_FIFO[FIFO_start+4'd1]; - end else if((fifoIsize==3) && (FIFO_SIZE > 2) && `EARLY_VALID_INSTRUCTION_)begin - VALID_INSTRUCTION <= 1; - INSTRUCTION[31:24] <= INPUT_FIFO[FIFO_start]; - INSTRUCTION[23:16] <= INPUT_FIFO[FIFO_start+4'd1]; - INSTRUCTION[15: 8] <= INPUT_FIFO[FIFO_start+4'd2]; - end else if(FIFO_SIZE>3)begin - VALID_INSTRUCTION <= 1; - INSTRUCTION[31:24] <= INPUT_FIFO[FIFO_start]; - INSTRUCTION[23:16] <= INPUT_FIFO[FIFO_start+4'd1]; - INSTRUCTION[15: 8] <= INPUT_FIFO[FIFO_start+4'd2]; - INSTRUCTION[ 7: 0] <= INPUT_FIFO[FIFO_start+4'd3]; - end + if((Isit1==1) && (FIFO_SIZE!=0) && `EARLY_VALID_INSTRUCTION_)begin + VALID_INSTRUCTION <= 1; + INSTRUCTION[31:24] <= INPUT_FIFO[FIFO_start]; + end else if((fifoIsize==2) && (FIFO_SIZE > 1) && `EARLY_VALID_INSTRUCTION_)begin + VALID_INSTRUCTION <= 1; + INSTRUCTION[31:24] <= INPUT_FIFO[FIFO_start]; + INSTRUCTION[23:16] <= INPUT_FIFO[FIFO_start+4'd1]; + end else if((fifoIsize==3) && (FIFO_SIZE > 2) && `EARLY_VALID_INSTRUCTION_)begin + VALID_INSTRUCTION <= 1; + INSTRUCTION[31:24] <= INPUT_FIFO[FIFO_start]; + INSTRUCTION[23:16] <= INPUT_FIFO[FIFO_start+4'd1]; + INSTRUCTION[15: 8] <= INPUT_FIFO[FIFO_start+4'd2]; + end else if(FIFO_SIZE>3)begin + VALID_INSTRUCTION <= 1; + INSTRUCTION[31:24] <= INPUT_FIFO[FIFO_start]; + INSTRUCTION[23:16] <= INPUT_FIFO[FIFO_start+4'd1]; + INSTRUCTION[15: 8] <= INPUT_FIFO[FIFO_start+4'd2]; + INSTRUCTION[ 7: 0] <= INPUT_FIFO[FIFO_start+4'd3]; end end diff --git a/system/execute.v b/system/execute.v index 866f883..1519774 100644 --- a/system/execute.v +++ b/system/execute.v @@ -20,7 +20,7 @@ module execute_unit ( /* GENERAL */ input clock, input reset ,input Wbit, input Sbit, input opcode_size,input [23:0] INSTRUCTION_BUFFER,input valid_input /* */ ,input [2:0] IN_MOD, input [2:0] OUT_MOD, input memio_address_select, input [15:0] ProgCount, input [2:0] RM, output reg [`ERROR_BITS-1:0] ERROR , input write /*TODO: REMOVE!!*/ - /* */ ,input set_initial_values,output stall + /* */ ,input set_initial_values, output reg work /* PARAM */ ,input [15:0] PARAM1_INIT, input [15:0] PARAM2_INIT /* STATE CONTROL */ ,output [`EXEC_STATE_BITS-1:0] _exec_state_, input [`EXEC_STATE_BITS-1:0] init_state /* ALU CONTROL */ ,input [1:0] in_alu_sel1, input [1:0] in_alu_sel2, input [`ALU_OP_BITS-1:0] ALU_OP, output [15:0] _ALU_O_ @@ -29,8 +29,6 @@ module execute_unit ( /* BIU */ ,output reg [15:0] BIU_ADDRESS_INPUT,output reg biu_write_request, output reg biu_read_request, input BIU_VALID_DATA, input [15:0] BIU_DATA, output reg biu_data_direction, output reg biu_jump_req ); -assign stall = work&valid_input; - assign _exec_state_ = exec_state; assign _ALU_O_ = ALU_O; @@ -75,6 +73,9 @@ always @(posedge valid_input) begin if(work == 0)begin exec_state <= init_state; work <= 1; + reg_write_we <= 1; + biu_jump_req <= 0; + use_exec_reg_addr <= 0; end end @@ -93,7 +94,6 @@ end `define unimpl_addressing_mode exec_state <= `EXEC_DONE;ERROR <= `ERR_UNIMPL_ADDRESSING_MODE; -reg work; always @(posedge clock) begin case (exec_state) `EXEC_RESET: begin @@ -107,10 +107,14 @@ always @(posedge clock) begin ERROR <= `ERR_NO_ERROR; end `EXEC_DONE:begin - work <= 0; reg_write_we <= 1; biu_jump_req <= 0; use_exec_reg_addr <= 0; + if(valid_input)begin + exec_state <= init_state; + work <= 1; + end else + work <= 0; end `EXEC_DE_LOAD_REG_TO_PARAM:begin work <= 1; @@ -240,12 +244,11 @@ always @(posedge clock) begin end end `EXEC_NEXT_INSTRUCTION:begin - work <= 1; + work <= 0; /*necessary for biu to see we went on another state from decode to give us a new instruction*/ exec_state <= `EXEC_DONE; end `EXEC_WRITE_ENTRY:begin - work <= 1; FLAGS[7:0] <= ALU_FLAGS[7:0]; case(OUT_MOD) 3'b000, @@ -294,35 +297,41 @@ always @(posedge clock) begin exec_state <= `EXEC_MEMIO_WRITE; end endcase + work <= 1; end 3'b011:begin reg_write_we <= 0; exec_state <= `EXEC_DONE; + work <= 0; end 3'b100:begin /*No output*/ exec_state <= `EXEC_DONE; + work <= 0; end 3'b101:begin /* Program Counter*/ BIU_ADDRESS_INPUT <= ALU_O[15:0]; biu_jump_req <= 1; exec_state <= `EXEC_DONE; + work <= 0; end 3'b110:begin /* SP Indirect write*/ reg_read_port1_addr <= 4'b1100; use_exec_reg_addr <= 1; exec_state <= `EXEC_MEMIO_WRITE; + work <= 1; end 3'b111:begin /* Write to PRAM1 (for microcode calculations) */ PARAM1 <= ALU_O; exec_state <= `EXEC_DONE; + work <= 0; end default:begin `unimpl_addressing_mode + work <= 1; end endcase end `EXEC_MEMIO_WRITE:begin - work <= 1; /* if memio_address_select == 0 ADDRESS: reg_read_port1_data DATA:ALU1_O */ /* if memio_address_select == 1 ADDRESS: ALU1_O DATA: reg_read_port1_data */ @@ -336,7 +345,9 @@ always @(posedge clock) begin if (write == 0) begin //TODO: don't do it that was or better yet don't do it at all somehow biu_write_request <= 0; exec_state <= `EXEC_DONE; - end + work <= 0; + end else + work <= 1; end `EXEC_HALT:begin diff --git a/system/processor.v b/system/processor.v index c7867be..5683f0b 100644 --- a/system/processor.v +++ b/system/processor.v @@ -72,11 +72,11 @@ assign OUT_MOD=DE_OUTPUT_sampled[49:47]; wire [`ALU_OP_BITS-1:0] ALU_OP; assign ALU_OP = DE_OUTPUT_sampled[42:40]; -wire stall; +wire work; execute_unit execute_unit ( /* GENERAL */ clock, reset, Wbit, Sbit, opcode_size, INSTRUCTION_BUFFER,valid_exec_data /* */ ,IN_MOD, OUT_MOD,memio_address_select, ProgCount, RM, EXEC_ERROR, write - /* */ ,set_initial_values,stall + /* */ ,set_initial_values,work /* PARAM */ ,PARAM1_INIT,PARAM2_INIT /* STATE CONTROL */ ,exec_state, next_state /* ALU CONTROL */ ,in_alu_sel1, in_alu_sel2, ALU_OP, ALU_O @@ -98,7 +98,7 @@ BIU BIU( /* */ ,external_data_bus,read,write,BHE,IOMEM /* Internal */ ,INSTRUCTION,VALID_INSTRUCTION,INSTRUCTION_LOCATION,biu_jump_req /* */ ,BIU_ADDRESS_INPUT,BIU_DATA,biu_write_request,biu_read_request,Wbit,BIU_VALID_DATA,MEM_OR_IO - /* */ ,state,SIMPLE_MICRO,stall + /* */ ,state,SIMPLE_MICRO ); assign BIU_DATA= biu_data_direction ? 16'hz : (memio_address_select ? reg_read_port1_data : ALU_O); @@ -195,8 +195,8 @@ always @(posedge clock) begin state <= `PROC_DE_STATE_ENTRY; end `PROC_DE_STATE_ENTRY:begin - if (!stall) begin - if(VALID_INSTRUCTION==1) begin + if(VALID_INSTRUCTION==1) begin + if(work==0) begin DE_OUTPUT_sampled <= DE_OUTPUT; if(SIMPLE_MICRO==0)begin @@ -221,16 +221,14 @@ always @(posedge clock) begin end end `PROC_WAIT:begin - if(!stall) begin - set_initial_values<=1; - valid_exec_data<=0; - state <= `PROC_DE_STATE_ENTRY; - if( SIMPLE_MICRO == 1 ) begin - ucode_seq_addr <= ucode_seq_addr_entry; /*Reused for next address*/ - if( ucode_seq_addr_entry == `UCODE_NO_INSTRUCTION )begin - /*Finished microcode*/ - SIMPLE_MICRO <= 0; - end + set_initial_values<=1; + valid_exec_data<=0; + state <= `PROC_DE_STATE_ENTRY; + if( SIMPLE_MICRO == 1 ) begin + ucode_seq_addr <= ucode_seq_addr_entry; /*Reused for next address*/ + if( ucode_seq_addr_entry == `UCODE_NO_INSTRUCTION )begin + /*Finished microcode*/ + SIMPLE_MICRO <= 0; end end end