9086/system/boot_code.asm

.ORG 0xFF00
start:
MOV SP,#STACK
MOV AX,#0x0000
MOV CX,#0x0000
MOV BX,#0x0000
CALL TEST_
ADD CX,#0xBEEF
ADD CX,#0x4111
mov AX,#0x00FF
inc AL
mov AX,#0x00FF
inc ax
ADD AX,#0x2200
MOV SI,#0x0101
MOV [SI],AX
inc [si]
inc [si]
inc [si]
dec [si]
dec cx
cmp CX,#0x00
MOV CH,#0x9A
inw #0x20
CMP AX,#0xABCD
jz WAZZ
mov al,#'0
out byte #0xA5
hlt
WAZZ:
mov al,#'1
out byte #0xA5
hlt
TEST_:
ADD AX,#0xDEAD
RET

;quick&dirty
PRINT_INT_HANDLE:
push AX
MOV AL,DL
out byte #0xA5
POP AX
iret

 .BLKB 10
STACK:

.ORG 0xFFF0
MOV AX,#0xFF00
JMP AX
Peripherals/Memory: Added support for the litedram DDR memory controller, created a new memory map and updated all relevant code and files including the addition of rudimentary wait state support for the cpu (BIU) 2023-12-03 19:24:12 +00:00			`.ORG 0xFF00`
It is Turing complete! Running the Mandelbrot renderer with the brainfuck interpreter. Improved addressing modes and added CMP immediate with register instruction 2023-02-15 03:53:05 +00:00			`start:`
Overhauled cpu frontend. Made memory byte addressable (necessary), cleaned up state machine and fixed small bug with MOV 2023-03-03 06:29:06 +00:00			`MOV SP,#STACK`
Removed now useless register init code and changed disas command name 2023-02-10 15:35:43 +00:00			`MOV AX,#0x0000`
			`MOV CX,#0x0000`
			`MOV BX,#0x0000`
Overhauled cpu frontend. Made memory byte addressable (necessary), cleaned up state machine and fixed small bug with MOV 2023-03-03 06:29:06 +00:00			`CALL TEST_`
Made the processor actually little-endian 2023-02-10 14:08:39 +00:00			`ADD CX,#0xBEEF`
			`ADD CX,#0x4111`
Improved ALU and added more INC and a DEC instruction 2023-02-11 14:43:53 +00:00			`mov AX,#0x00FF`
			`inc AL`
			`mov AX,#0x00FF`
			`inc ax`
Made the processor actually little-endian 2023-02-10 14:08:39 +00:00			`ADD AX,#0x2200`
It is Turing complete! Running the Mandelbrot renderer with the brainfuck interpreter. Improved addressing modes and added CMP immediate with register instruction 2023-02-15 03:53:05 +00:00			`MOV SI,#0x0101`
Added 16bit unaligned register indirect writes, fixed some MOV bugs, clean up code names and data flow 2023-02-15 01:28:02 +00:00			`MOV [SI],AX`
It is Turing complete! Running the Mandelbrot renderer with the brainfuck interpreter. Improved addressing modes and added CMP immediate with register instruction 2023-02-15 03:53:05 +00:00			`inc [si]`
			`inc [si]`
			`inc [si]`
			`dec [si]`
Improved build system and project directory structure 2023-02-16 01:46:22 +00:00			`dec cx`
It is Turing complete! Running the Mandelbrot renderer with the brainfuck interpreter. Improved addressing modes and added CMP immediate with register instruction 2023-02-15 03:53:05 +00:00			`cmp CX,#0x00`
Added bitwise TEST instruction 2023-02-24 10:08:01 +00:00			`MOV CH,#0x9A`
Processor/Instructions: Added support for the IN <immediate> instruction. Also changed some stuff in system.v to add more devices in the IO/Memory space 2023-11-25 04:11:51 +00:00			`inw #0x20`
Peripherals/Memory: Added support for the litedram DDR memory controller, created a new memory map and updated all relevant code and files including the addition of rudimentary wait state support for the cpu (BIU) 2023-12-03 19:24:12 +00:00			`CMP AX,#0xABCD`
Added bitwise TEST instruction 2023-02-24 10:08:01 +00:00			`jz WAZZ`
Processor/Instructions: Added support for the IN <immediate> instruction. Also changed some stuff in system.v to add more devices in the IO/Memory space 2023-11-25 04:11:51 +00:00			`mov al,#'0`
			`out byte #0xA5`
Added bitwise TEST instruction 2023-02-24 10:08:01 +00:00			`hlt`
			`WAZZ:`
Processor/Instructions: Added support for the IN <immediate> instruction. Also changed some stuff in system.v to add more devices in the IO/Memory space 2023-11-25 04:11:51 +00:00			`mov al,#'1`
Peripherals/Memory: Added support for the litedram DDR memory controller, created a new memory map and updated all relevant code and files including the addition of rudimentary wait state support for the cpu (BIU) 2023-12-03 19:24:12 +00:00			`out byte #0xA5`
Added bitwise TEST instruction 2023-02-24 10:08:01 +00:00			`hlt`
Overhauled cpu frontend. Made memory byte addressable (necessary), cleaned up state machine and fixed small bug with MOV 2023-03-03 06:29:06 +00:00			`TEST_:`
			`ADD AX,#0xDEAD`
			`RET`

Improved DOS char print code 2023-03-14 07:20:30 +00:00			`;quick&dirty`
Added the OUT instruction to be able to properly address I/O and moved printing logic to a device on the I/O space. Also added IRET which is basically just a RET in this case 2023-03-09 06:02:41 +00:00			`PRINT_INT_HANDLE:`
			`push AX`
			`MOV AL,DL`
			`out byte #0xA5`
			`POP AX`
			`iret`

Overhauled cpu frontend. Made memory byte addressable (necessary), cleaned up state machine and fixed small bug with MOV 2023-03-03 06:29:06 +00:00			`.BLKB 10`
			`STACK:`
Added partial support for the software interrupt INT instruction 2023-03-08 07:26:28 +00:00
			`.ORG 0xFFF0`
Peripherals/Memory: Added support for the litedram DDR memory controller, created a new memory map and updated all relevant code and files including the addition of rudimentary wait state support for the cpu (BIU) 2023-12-03 19:24:12 +00:00			`MOV AX,#0xFF00`
Added partial support for the software interrupt INT instruction 2023-03-08 07:26:28 +00:00			`JMP AX`