9086/cpu/gtkwave_savefile.gtkw

[*]
[*] GTKWave Analyzer v3.3.104 (w)1999-2020 BSI
[*] Thu Feb  9 14:44:08 2023
[*]
[dumpfile] "/home/user/UNI_DATA/COMS30046_2022_TB-2/projects/9086/cpu/test.lx2"
[dumpfile_mtime] "Thu Feb  9 14:43:59 2023"
[dumpfile_size] 757
[savefile] "/home/user/UNI_DATA/COMS30046_2022_TB-2/projects/9086/cpu/gtkwave_savefile.gtkw"
[timestart] 0
[size] 1630 1059
[pos] -1 -1
*-22.795050 2010000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[treeopen] tb.
[sst_width] 221
[signals_width] 293
[sst_expanded] 1
[sst_vpaned_height] 313
@29
tb.p.clock[0]
@28
tb.p.reset[0]
@22
tb.p.state[3:0]
tb.p.external_address_bus[19:0]
tb.p.external_data_bus[15:0]
tb.p.CIR[15:0]
@28
tb.p.EXCEPTION[0]
tb.p.ADD_INST[0]
tb.p.INC_INST[0]
@22
tb.p.PARAM1[15:0]
[pattern_trace] 1
[pattern_trace] 0
Basic start for the control block 2023-02-08 09:18:00 +00:00			`[*]`
			`[*] GTKWave Analyzer v3.3.104 (w)1999-2020 BSI`
Added primitive decode stage, improved state handling and fixed CIR register 2023-02-09 14:46:21 +00:00			`[*] Thu Feb 9 14:44:08 2023`
Basic start for the control block 2023-02-08 09:18:00 +00:00			`[*]`
			`[dumpfile] "/home/user/UNI_DATA/COMS30046_2022_TB-2/projects/9086/cpu/test.lx2"`
Added primitive decode stage, improved state handling and fixed CIR register 2023-02-09 14:46:21 +00:00			`[dumpfile_mtime] "Thu Feb 9 14:43:59 2023"`
			`[dumpfile_size] 757`
Basic start for the control block 2023-02-08 09:18:00 +00:00			`[savefile] "/home/user/UNI_DATA/COMS30046_2022_TB-2/projects/9086/cpu/gtkwave_savefile.gtkw"`
			`[timestart] 0`
Added primitive decode stage, improved state handling and fixed CIR register 2023-02-09 14:46:21 +00:00			`[size] 1630 1059`
Basic start for the control block 2023-02-08 09:18:00 +00:00			`[pos] -1 -1`
Added primitive decode stage, improved state handling and fixed CIR register 2023-02-09 14:46:21 +00:00			`*-22.795050 2010000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1`
Basic start for the control block 2023-02-08 09:18:00 +00:00			`[treeopen] tb.`
			`[sst_width] 221`
Added ROM, address and data buses and primitive program counter 2023-02-08 11:57:22 +00:00			`[signals_width] 293`
Basic start for the control block 2023-02-08 09:18:00 +00:00			`[sst_expanded] 1`
			`[sst_vpaned_height] 313`
Implemented a basic Instruction Fetch stage and added some examples in the 8086 doc 2023-02-08 23:59:06 +00:00			`@29`
Added primitive decode stage, improved state handling and fixed CIR register 2023-02-09 14:46:21 +00:00			`tb.p.clock[0]`
Implemented a basic Instruction Fetch stage and added some examples in the 8086 doc 2023-02-08 23:59:06 +00:00			`@28`
Added primitive decode stage, improved state handling and fixed CIR register 2023-02-09 14:46:21 +00:00			`tb.p.reset[0]`
Added ROM, address and data buses and primitive program counter 2023-02-08 11:57:22 +00:00			`@22`
Added primitive decode stage, improved state handling and fixed CIR register 2023-02-09 14:46:21 +00:00			`tb.p.state[3:0]`
Added ROM, address and data buses and primitive program counter 2023-02-08 11:57:22 +00:00			`tb.p.external_address_bus[19:0]`
			`tb.p.external_data_bus[15:0]`
Added primitive decode stage, improved state handling and fixed CIR register 2023-02-09 14:46:21 +00:00			`tb.p.CIR[15:0]`
Implemented a basic Instruction Fetch stage and added some examples in the 8086 doc 2023-02-08 23:59:06 +00:00			`@28`
Added primitive decode stage, improved state handling and fixed CIR register 2023-02-09 14:46:21 +00:00			`tb.p.EXCEPTION[0]`
			`tb.p.ADD_INST[0]`
			`tb.p.INC_INST[0]`
			`@22`
			`tb.p.PARAM1[15:0]`
Basic start for the control block 2023-02-08 09:18:00 +00:00			`[pattern_trace] 1`
			`[pattern_trace] 0`