(Tim) Efthimis Kritikos a166efec9c Moved clock generator to the testbench		2023-02-09 14:51:50 +00:00
..
boot_code.txt	Implemented a basic Instruction Fetch stage and added some examples in the 8086 doc	2023-02-08 23:59:06 +00:00
gtkwave_savefile.gtkw	Added primitive decode stage, improved state handling and fixed CIR register	2023-02-09 14:46:21 +00:00
Makefile	Added ROM, address and data buses and primitive program counter	2023-02-08 11:57:22 +00:00
memory.v	Added ROM, address and data buses and primitive program counter	2023-02-08 11:57:22 +00:00
proc_state_def.v	Added primitive decode stage, improved state handling and fixed CIR register	2023-02-09 14:46:21 +00:00
processor.v	Moved clock generator to the testbench	2023-02-09 14:51:50 +00:00
testbench.v	Moved clock generator to the testbench	2023-02-09 14:51:50 +00:00