2023-02-13 16:49:17 +00:00
|
|
|
/* testbench.v - Testbench for the 9086 CPU
|
|
|
|
|
|
|
|
This file is part of the 9086 project.
|
|
|
|
|
|
|
|
Copyright (c) 2023 Efthymios Kritikos
|
|
|
|
|
|
|
|
This program is free software: you can redistribute it and/or modify
|
|
|
|
it under the terms of the GNU General Public License as published by
|
|
|
|
the Free Software Foundation, either version 3 of the License, or
|
|
|
|
(at your option) any later version.
|
|
|
|
|
|
|
|
This program is distributed in the hope that it will be useful,
|
|
|
|
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
|
|
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
|
|
GNU General Public License for more details.
|
|
|
|
|
|
|
|
You should have received a copy of the GNU General Public License
|
|
|
|
along with this program. If not, see <http://www.gnu.org/licenses/>. */
|
|
|
|
|
2023-02-09 14:51:50 +00:00
|
|
|
`timescale 1ns/1ps
|
|
|
|
|
2023-02-08 09:18:00 +00:00
|
|
|
module tb;
|
2023-02-08 12:07:42 +00:00
|
|
|
wire clock;
|
|
|
|
reg reset;
|
|
|
|
reg clk_enable;
|
|
|
|
wire [19:0]address_bus;
|
|
|
|
wire [15:0]data_bus;
|
2023-03-04 08:37:43 +00:00
|
|
|
wire rd,wr,HALT;
|
2023-02-11 01:05:19 +00:00
|
|
|
wire ERROR;
|
2023-03-03 06:29:06 +00:00
|
|
|
wire IOMEM;
|
2023-02-08 09:18:00 +00:00
|
|
|
|
2023-03-04 08:37:43 +00:00
|
|
|
system system( .clock(clock),
|
|
|
|
.reset(reset),
|
|
|
|
.address_bus(address_bus),
|
|
|
|
.data_bus(data_bus),
|
|
|
|
.rd(rd),
|
|
|
|
.wr(wr),
|
|
|
|
.HALT(HALT),
|
|
|
|
.ERROR(ERROR),
|
|
|
|
.IOMEM(IOMEM)
|
|
|
|
);
|
2023-02-08 09:18:00 +00:00
|
|
|
|
2023-02-08 23:59:06 +00:00
|
|
|
`define CPU_SPEED 1000
|
|
|
|
|
2023-02-08 12:07:42 +00:00
|
|
|
clock_gen #(.FREQ(1000)) u1(clk_enable, clock);
|
2023-02-08 11:57:22 +00:00
|
|
|
|
2023-02-10 18:20:28 +00:00
|
|
|
integer cycles=0;
|
2023-02-08 09:18:00 +00:00
|
|
|
|
2023-02-16 01:46:22 +00:00
|
|
|
string memdump_name;
|
2023-02-08 12:07:42 +00:00
|
|
|
initial begin
|
2023-02-16 01:46:22 +00:00
|
|
|
string waveform_name;
|
2023-02-16 23:26:32 +00:00
|
|
|
if($value$plusargs("WAVEFORM=%s",waveform_name))begin
|
|
|
|
$dumpfile(waveform_name);
|
2023-03-04 08:37:43 +00:00
|
|
|
$dumpvars(0,system);
|
2023-02-16 01:46:22 +00:00
|
|
|
end
|
2023-02-19 00:20:53 +00:00
|
|
|
clk_enable = 1;
|
2023-02-08 09:18:00 +00:00
|
|
|
|
2023-03-04 06:22:28 +00:00
|
|
|
reset = 1;
|
|
|
|
#(`CPU_SPEED*2)
|
|
|
|
reset = 0;
|
|
|
|
#($random%1000)
|
2023-02-09 14:46:21 +00:00
|
|
|
#(`CPU_SPEED)
|
2023-02-08 12:07:42 +00:00
|
|
|
reset = 1;
|
2023-02-10 18:20:28 +00:00
|
|
|
end
|
2023-02-08 12:07:42 +00:00
|
|
|
|
2023-02-10 18:20:28 +00:00
|
|
|
|
2023-02-11 01:05:19 +00:00
|
|
|
always @(posedge ERROR) begin
|
2023-02-13 15:24:21 +00:00
|
|
|
clk_enable <= 0;
|
2023-02-11 01:05:19 +00:00
|
|
|
$display("PROCESSOR RUN INTO AN ERROR.\nCycles run for: %d",cycles);
|
2023-02-16 23:26:32 +00:00
|
|
|
if($value$plusargs("MEMDUMP=%s",memdump_name))begin
|
2023-03-04 08:37:43 +00:00
|
|
|
$writememh(memdump_name, system.sysmem.memory,0,32767);
|
2023-02-16 23:26:32 +00:00
|
|
|
end
|
2023-02-11 01:05:19 +00:00
|
|
|
#(`CPU_SPEED) //Just for the waveform
|
|
|
|
$finish;
|
|
|
|
end
|
|
|
|
|
2023-02-10 18:20:28 +00:00
|
|
|
always @(posedge clock)begin
|
|
|
|
if(reset==1)
|
|
|
|
cycles=cycles+1;
|
2023-03-04 06:22:28 +00:00
|
|
|
else
|
|
|
|
cycles=0;
|
2023-02-10 18:20:28 +00:00
|
|
|
end
|
|
|
|
|
2023-02-08 09:18:00 +00:00
|
|
|
endmodule
|
2023-02-09 14:51:50 +00:00
|
|
|
|
|
|
|
|
|
|
|
/*Clock generator*/
|
|
|
|
module clock_gen (input enable, output reg clk);
|
|
|
|
|
|
|
|
parameter FREQ = 1000; // in HZ
|
|
|
|
parameter PHASE = 0; // in degrees
|
|
|
|
parameter DUTY = 50; // in percentage
|
|
|
|
|
|
|
|
real clk_pd = 1.0/FREQ * 1000000; // convert to ms
|
|
|
|
real clk_on = DUTY/100.0 * clk_pd;
|
|
|
|
real clk_off = (100.0 - DUTY)/100.0 * clk_pd;
|
|
|
|
real quarter = clk_pd/4;
|
|
|
|
real start_dly = quarter * PHASE/90;
|
|
|
|
|
|
|
|
reg start_clk;
|
|
|
|
|
|
|
|
initial begin
|
|
|
|
end
|
|
|
|
|
2023-02-13 16:49:17 +00:00
|
|
|
// Initialise variables to zero
|
2023-02-09 14:51:50 +00:00
|
|
|
initial begin
|
2023-02-19 00:20:53 +00:00
|
|
|
clk = 0;
|
|
|
|
start_clk = 0;
|
2023-02-09 14:51:50 +00:00
|
|
|
end
|
|
|
|
|
|
|
|
// When clock is enabled, delay driving the clock to one in order
|
|
|
|
// to achieve the phase effect. start_dly is configured to the
|
|
|
|
// correct delay for the configured phase. When enable is 0,
|
|
|
|
// allow enough time to complete the current clock period
|
|
|
|
always @ (posedge enable or negedge enable) begin
|
|
|
|
if (enable) begin
|
|
|
|
#(start_dly) start_clk = 1;
|
|
|
|
end else begin
|
|
|
|
#(start_dly) start_clk = 0;
|
|
|
|
end
|
|
|
|
end
|
|
|
|
|
|
|
|
// Achieve duty cycle by a skewed clock on/off time and let this
|
|
|
|
// run as long as the clocks are turned on.
|
|
|
|
always @(posedge start_clk) begin
|
|
|
|
if (start_clk) begin
|
|
|
|
clk = 1;
|
|
|
|
|
|
|
|
while (start_clk) begin
|
|
|
|
#(clk_on) clk = 0;
|
|
|
|
#(clk_off) clk = 1;
|
|
|
|
end
|
|
|
|
|
|
|
|
clk = 0;
|
|
|
|
end
|
|
|
|
end
|
|
|
|
endmodule
|