9086/cpu/testbench.v

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module tb;
wire clock;
reg reset;
reg clk_enable;
wire [19:0]address_bus;
wire [15:0]data_bus;
wire rd,wr,romcs;
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processor p(clock,reset,address_bus,data_bus,rd,wr);
rom bootrom(address_bus,data_bus,rd,romcs);
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clock_gen #(.FREQ(1000)) u1(clk_enable, clock);
assign romcs=0;
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initial begin
$dumpfile("test.lx2");
$dumpvars(0,p);
clk_enable <= 1;
#($random%500)
reset = 0;
#(100)
reset = 1;
#(10000)
#50 $finish;
end
endmodule