9086/gtkwave_savefile.gtkw

[*]
[*] GTKWave Analyzer v3.3.111 (w)1999-2020 BSI
[*] Thu Mar  9 04:20:33 2023
[*]
[dumpfile] "/home/user/9086/system/boot_code.fst"
[dumpfile_mtime] "Thu Mar  9 04:18:18 2023"
[dumpfile_size] 8510
[savefile] "/home/user/9086/gtkwave_savefile.gtkw"
[timestart] 198700000000
[size] 1236 1017
[pos] -1 -1
*-34.595051 280500000000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[treeopen] TOP.
[treeopen] TOP.system.
[sst_width] 221
[signals_width] 293
[sst_expanded] 1
[sst_vpaned_height] 312
@28
TOP.system.clock
TOP.system.reset
TOP.system.p.state[5:0]
@22
TOP.system.p.ucode_seq_addr[4:0]
TOP.system.address_bus[19:0]
TOP.system.data_bus[15:0]
TOP.system.p.CIR[15:0]
TOP.system.p.PARAM1[15:0]
TOP.system.p.PARAM2[15:0]
@28
TOP.system.p.read
TOP.system.p.write
@29
TOP.system.IOMEM
@22
TOP.system.p.ALU_1A[15:0]
TOP.system.p.ALU_1B[15:0]
TOP.system.p.ALU_1O[15:0]
@28
TOP.system.p.ERROR
TOP.system.p.HALT
[pattern_trace] 1
[pattern_trace] 0
Basic start for the control block 2023-02-08 09:18:00 +00:00			`[*]`
Wrote a more complete testbench for verilator, switched from lx2 to fst and fixed cpu clock frequency calculation 2023-03-05 00:10:55 +00:00			`[*] GTKWave Analyzer v3.3.111 (w)1999-2020 BSI`
Added the OUT instruction to be able to properly address I/O and moved printing logic to a device on the I/O space. Also added IRET which is basically just a RET in this case 2023-03-09 06:02:41 +00:00			`[*] Thu Mar 9 04:20:33 2023`
Basic start for the control block 2023-02-08 09:18:00 +00:00			`[*]`
Added the OUT instruction to be able to properly address I/O and moved printing logic to a device on the I/O space. Also added IRET which is basically just a RET in this case 2023-03-09 06:02:41 +00:00			`[dumpfile] "/home/user/9086/system/boot_code.fst"`
			`[dumpfile_mtime] "Thu Mar 9 04:18:18 2023"`
			`[dumpfile_size] 8510`
Wrote a more complete testbench for verilator, switched from lx2 to fst and fixed cpu clock frequency calculation 2023-03-05 00:10:55 +00:00			`[savefile] "/home/user/9086/gtkwave_savefile.gtkw"`
Added the OUT instruction to be able to properly address I/O and moved printing logic to a device on the I/O space. Also added IRET which is basically just a RET in this case 2023-03-09 06:02:41 +00:00			`[timestart] 198700000000`
			`[size] 1236 1017`
Basic start for the control block 2023-02-08 09:18:00 +00:00			`[pos] -1 -1`
Added the OUT instruction to be able to properly address I/O and moved printing logic to a device on the I/O space. Also added IRET which is basically just a RET in this case 2023-03-09 06:02:41 +00:00			`*-34.595051 280500000000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1`
Wrote a more complete testbench for verilator, switched from lx2 to fst and fixed cpu clock frequency calculation 2023-03-05 00:10:55 +00:00			`[treeopen] TOP.`
			`[treeopen] TOP.system.`
Basic start for the control block 2023-02-08 09:18:00 +00:00			`[sst_width] 221`
Added ROM, address and data buses and primitive program counter 2023-02-08 11:57:22 +00:00			`[signals_width] 293`
Basic start for the control block 2023-02-08 09:18:00 +00:00			`[sst_expanded] 1`
Added Microcode support, Stack, implemented the CALL instruction in microcode and grouped the wires on the decoder module 2023-02-22 01:28:23 +00:00			`[sst_vpaned_height] 312`
Implemented a basic Instruction Fetch stage and added some examples in the 8086 doc 2023-02-08 23:59:06 +00:00			`@28`
Wrote a more complete testbench for verilator, switched from lx2 to fst and fixed cpu clock frequency calculation 2023-03-05 00:10:55 +00:00			`TOP.system.clock`
			`TOP.system.reset`
			`TOP.system.p.state[5:0]`
Added a very basic execution stage, registers and a very crude adder for ALU. It finally executes instructions! 2023-02-09 20:16:50 +00:00			`@22`
Added the OUT instruction to be able to properly address I/O and moved printing logic to a device on the I/O space. Also added IRET which is basically just a RET in this case 2023-03-09 06:02:41 +00:00			`TOP.system.p.ucode_seq_addr[4:0]`
Wrote a more complete testbench for verilator, switched from lx2 to fst and fixed cpu clock frequency calculation 2023-03-05 00:10:55 +00:00			`TOP.system.address_bus[19:0]`
			`TOP.system.data_bus[15:0]`
			`TOP.system.p.CIR[15:0]`
			`TOP.system.p.PARAM1[15:0]`
			`TOP.system.p.PARAM2[15:0]`
Added support for writing to memory 2023-02-14 13:13:40 +00:00			`@28`
Wrote a more complete testbench for verilator, switched from lx2 to fst and fixed cpu clock frequency calculation 2023-03-05 00:10:55 +00:00			`TOP.system.p.read`
			`TOP.system.p.write`
Added the OUT instruction to be able to properly address I/O and moved printing logic to a device on the I/O space. Also added IRET which is basically just a RET in this case 2023-03-09 06:02:41 +00:00			`@29`
			`TOP.system.IOMEM`
Wrote a more complete testbench for verilator, switched from lx2 to fst and fixed cpu clock frequency calculation 2023-03-05 00:10:55 +00:00			`@22`
			`TOP.system.p.ALU_1A[15:0]`
			`TOP.system.p.ALU_1B[15:0]`
			`TOP.system.p.ALU_1O[15:0]`
			`@28`
			`TOP.system.p.ERROR`
			`TOP.system.p.HALT`
Basic start for the control block 2023-02-08 09:18:00 +00:00			`[pattern_trace] 1`
			`[pattern_trace] 0`