(Tim) Efthimis Kritikos Efthimis
0 Followers · 0 Following
Repositories
5
 Projects Packages Public Activity Starred Repositories
Efthimis pushed to master at Efthimis/9086 2023-02-15 01:27:53 +00:00
f4d28cf4c8 Added 16bit unaligned register indirect writes, fixed some MOV bugs, clean up code names and data flow
Efthimis pushed to master at Efthimis/9086 2023-02-14 15:49:55 +00:00
c3563457c5 Finished MOV Reg/Mem to/from register
Efthimis pushed to master at Efthimis/9086 2023-02-14 14:48:24 +00:00
f97f4625e6 Added unconditional jumps and support for signed addition
Efthimis pushed to master at Efthimis/9086 2023-02-14 13:13:36 +00:00
037f6dd7da Added support for writing to memory
Efthimis pushed to master at Efthimis/9086 2023-02-13 16:49:15 +00:00
7c1067088c Properly licensed the project and run it through aspell
0d4221f9de Added config file (mainly for debug verbosity) and kind of patched some weird behaviour when clock is stopped
Compare 2 commits »
Efthimis pushed to master at Efthimis/9086 2023-02-13 10:36:31 +00:00
16e02e0788 Added conditional jump support!
Efthimis pushed to master at Efthimis/9086 2023-02-12 01:30:48 +00:00
923bf07c72 Fixed ALU bug and added missed updates to the Wbit
Efthimis pushed to master at Efthimis/9086 2023-02-12 01:05:35 +00:00
c684348e38 Implemented a CMP instruction and the some of the flags
Efthimis pushed to master at Efthimis/9086 2023-02-11 20:28:12 +00:00
0901af23db Added support for some register indirect addressing modes. Also added documentation comments and did some general cleanup
Efthimis pushed to master at Efthimis/9086 2023-02-11 14:43:55 +00:00
85bf886223 Improved ALU and added more INC and a DEC instruction
Efthimis pushed to master at Efthimis/9086 2023-02-11 13:41:18 +00:00
be06244021 Improved register file addressing and printout
Efthimis pushed to master at Efthimis/9086 2023-02-11 01:16:47 +00:00
abe263aa57 Removed erroneous file
Efthimis pushed to master at Efthimis/9086 2023-02-11 01:13:37 +00:00
d7eb4f36c0 Wrote very basic brainfuck interpreter in 8086 asm to work on making it run and prove Turing completeness
fd31eb704c Made the simulation stop at an unrecognised instruction or other error
Compare 2 commits »
Efthimis pushed to master at Efthimis/9086 2023-02-10 18:21:41 +00:00
fc4ecdb8d2 Added HLT instruction, made testbench count total clock cycles and write memdump and fixed reset timing
Efthimis pushed to master at Efthimis/9086 2023-02-10 15:41:55 +00:00
cd918302cc Removed now useless register init code and changed disas command name
bba230fbce Added the MOV immediate to register instruction
Compare 2 commits »
Efthimis pushed to master at Efthimis/9086 2023-02-10 14:39:38 +00:00
e685c52ddd Improved instruction decoding
6561018206 Made the processor actually little-endian
Compare 2 commits »
Efthimis pushed to master at Efthimis/9086 2023-02-10 13:32:54 +00:00
19fcf11f63 Still hadn't added all files from the assembler commit. Also fixed .gitignore
Efthimis pushed to master at Efthimis/9086 2023-02-10 13:27:17 +00:00
57b159bce3 Wrote a README
2595dc1b6c Hadn't added all files to previous commit
Compare 2 commits »
Efthimis pushed to master at Efthimis/Testing 2023-02-10 13:21:28 +00:00
78facba81e Heading test
Efthimis pushed to master at Efthimis/Testing 2023-02-10 13:02:01 +00:00
28e731d767 more testing