- https://efthimiskritikos.com/
- Joined on
2023-02-04
Block a user
82baacfd5b
Fixed race condition giving garbage data on debug register write prints and ordering of reg write and instr fetch debug prints
11624ca2d2
Added the OUT instruction to be able to properly address I/O and moved printing logic to a device on the I/O space. Also added IRET which is basically just a RET in this case
99cbc49e95
Wrote a more complete testbench for verilator, switched from lx2 to fst and fixed cpu clock frequency calculation
ba52ff89e6
Fixed most problems verilator's linter found
59ec1b7a15
Removed remnants of the old memory addressing system
f60084344e
Overhauled cpu frontend. Made memory byte addressable (necessary), cleaned up state machine and fixed small bug with MOV