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(Tim) Efthimis Kritikos 2023-11-07 14:23:36 +00:00
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@ -14,6 +14,7 @@ A CPU that aims to be binary compatible with the 8086 ISA, focused on optimisati
* [ ] Is Out of Order
* [ ] Is superscalar
* [X] Has been successfully synthesized
* [ ] Has a comprehensive testing framework
### High level design overview
@ -21,7 +22,7 @@ A CPU that aims to be binary compatible with the 8086 ISA, focused on optimisati
### Simulating it
Both Verilator and Icarus Verilog can be used for simulation. You can select which one you want with the SIM variable on [./common.mk](./common.mk).
This list shows the software needed and the versions used during development
This list shows the software needed and the versions used during development :
* Icarus Verilog : version 12.0 OR **(preferred)** Verilator : 5.016
* bin86 : 0.16.21
@ -34,7 +35,11 @@ After that you can run `make` on the top level directory and it should build eve
### Synthesis and bitstream creation ( for FPGAs )
Synthesis is based on Yosys. You need to set FPGA\_BOARD in [./common.mk](./common.mk) to the name of a directory inside [./system/fpga\_config/](system/fpga_config/). You should also check inside your board directory for config.mk for further board-specific configuration options. Then you can run `make upload` in the top level directory and it should create the bitstream and upload it.
This list shows the software needed and the versions used during development
These are the currently supported fpga boards:
* OrangeCrab r0.2.1
This list shows the software needed and the versions used during development :
* yosys : 0.35
* bin86 : 0.16.21