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test.md
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test.md
@ -14,6 +14,7 @@ A CPU that aims to be binary compatible with the 8086 ISA, focused on optimisati
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* [ ] Is Out of Order
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* [ ] Is Out of Order
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* [ ] Is superscalar
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* [ ] Is superscalar
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* [X] Has been successfully synthesized
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* [X] Has been successfully synthesized
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* [ ] Has a comprehensive testing framework
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### High level design overview
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### High level design overview
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@ -21,7 +22,7 @@ A CPU that aims to be binary compatible with the 8086 ISA, focused on optimisati
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### Simulating it
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### Simulating it
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Both Verilator and Icarus Verilog can be used for simulation. You can select which one you want with the SIM variable on [./common.mk](./common.mk).
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Both Verilator and Icarus Verilog can be used for simulation. You can select which one you want with the SIM variable on [./common.mk](./common.mk).
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This list shows the software needed and the versions used during development
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This list shows the software needed and the versions used during development :
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* Icarus Verilog : version 12.0 OR **(preferred)** Verilator : 5.016
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* Icarus Verilog : version 12.0 OR **(preferred)** Verilator : 5.016
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* bin86 : 0.16.21
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* bin86 : 0.16.21
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@ -34,7 +35,11 @@ After that you can run `make` on the top level directory and it should build eve
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### Synthesis and bitstream creation ( for FPGAs )
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### Synthesis and bitstream creation ( for FPGAs )
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Synthesis is based on Yosys. You need to set FPGA\_BOARD in [./common.mk](./common.mk) to the name of a directory inside [./system/fpga\_config/](system/fpga_config/). You should also check inside your board directory for config.mk for further board-specific configuration options. Then you can run `make upload` in the top level directory and it should create the bitstream and upload it.
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Synthesis is based on Yosys. You need to set FPGA\_BOARD in [./common.mk](./common.mk) to the name of a directory inside [./system/fpga\_config/](system/fpga_config/). You should also check inside your board directory for config.mk for further board-specific configuration options. Then you can run `make upload` in the top level directory and it should create the bitstream and upload it.
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This list shows the software needed and the versions used during development
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These are the currently supported fpga boards:
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* OrangeCrab r0.2.1
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This list shows the software needed and the versions used during development :
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* yosys : 0.35
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* yosys : 0.35
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* bin86 : 0.16.21
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* bin86 : 0.16.21
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