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test.md
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test.md
@ -32,7 +32,7 @@ Specifically this list shows the software needed and the versions used during de
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After that you can run `make` on the top level directory and it should build everything and start the simulation
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### Synthesis and bitstream creation ( for FPGAs )
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Synthesis is based on yosys. You need to select your board in [common.mk](./common.mk) which is basically a directory inside [system/fpga\_config/](system/fpga_config/) which had configuration files specifically for that board. You should also check inside your board directory for config.mk for further configuration options specific to the board. Then you can run `make upload` in the top level directory and it should create the bitstream and upload it.
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Synthesis is based on yosys. You need to select your board in [common.mk](./common.mk) which is basically a directory inside [system/fpga\_config/](system/fpga_config/) which has configuration files specific to that board. You should also check inside your board directory for config.mk for further board-specific configuration options. Then you can run `make upload` in the top level directory and it should create the bitstream and upload it.
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This list shows the software needed and the versions used during development
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@ -42,12 +42,12 @@ This list shows the software needed and the versions used during development
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* xxd : 2022-01-14
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* POSIX coreutils : GNU coreutils 9.4
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For ECP5 FPGAs:
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Additionally, for ECP5 FPGAs:
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* prjtrellis : 1.4 ( database commit 4dda149b9e4f1753ebc8b011ece2fe794be1281a )
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* nextpnr : 0.6
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For FPGAs using the [foboot](https://github.com/im-tomu/foboot) bootloader
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Additionally, for FPGAs using the [foboot](https://github.com/im-tomu/foboot) bootloader
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* dfu-util : 0.11
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