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(Tim) Efthimis Kritikos 2023-11-07 13:44:09 +00:00
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test.md
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@ -32,7 +32,7 @@ Specifically this list shows the software needed and the versions used during de
After that you can run `make` on the top level directory and it should build everything and start the simulation
### Synthesis and bitstream creation ( for FPGAs )
Synthesis is based on yosys. You need to select your board in [common.mk](./common.mk) which is basically a directory inside [system/fpga\_config/](system/fpga_config/) which has configuration files specific to that board. You should also check inside your board directory for config.mk for further board-specific configuration options. Then you can run `make upload` in the top level directory and it should create the bitstream and upload it.
Synthesis is based on Yosys. You need to select your board in [common.mk](./common.mk) which is the name of a directory inside inside [system/fpga\_config/](system/fpga_config/) which has configuration files specific to that board. You should also check inside your board directory for config.mk for further board-specific configuration options. Then you can run `make upload` in the top level directory and it should create the bitstream and upload it.
This list shows the software needed and the versions used during development
@ -51,7 +51,7 @@ Additionally, for FPGAs using the [foboot](https://github.com/im-tomu/foboot) bo
* dfu-util : 0.11
### License
### License and Copyright
All parts of this project and files in this repository are licensed under the GNU General Public License version 3 or later
Efthymios Kritikos is the copyright owner for all files except the following:
@ -68,3 +68,4 @@ The version name consist of three numbers:
1. Patch level
For example v1.3.2 aims to support 80186 code, is on the fourth milestone and has 2 bug fixes since the milestone was reached.
A "-dev" suffix denotes that the code is in the process to become that version, so in-between that and the previous.