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(Tim) Efthimis Kritikos 2023-11-07 13:47:15 +00:00
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@ -32,7 +32,7 @@ Specifically this list shows the software needed and the versions used during de
After that you can run `make` on the top level directory and it should build everything and start the simulation
### Synthesis and bitstream creation ( for FPGAs )
Synthesis is based on Yosys. You need to select your board in [common.mk](./common.mk) which is the name of a directory inside inside [system/fpga\_config/](system/fpga_config/) which has configuration files specific to that board. You should also check inside your board directory for config.mk for further board-specific configuration options. Then you can run `make upload` in the top level directory and it should create the bitstream and upload it.
Synthesis is based on Yosys. You need to set FPGA\_BOARD in [common.mk](./common.mk) to the name of a directory inside [system/fpga\_config/](system/fpga_config/). You should also check inside your board directory for config.mk for further board-specific configuration options. Then you can run `make upload` in the top level directory and it should create the bitstream and upload it.
This list shows the software needed and the versions used during development